JPS5997184A - Image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device, and particularly to a processing device using an image data memory.

Tesque scanning cathode ray tube (hereinafter referred to as CRT)
The application of displaying information stored in a refresh memory by using it as a display device is expanding. Currently, CRTs display letters, numbers, graphic figures,
It has become possible to display a lot of information, including kanji. However, there is a demand for more advanced display functions, such as a function that divides the screen into upper, lower, left and right areas, and displays independent content in each area. The operation of a conventional display device will be explained using the drawings. FIG. 1 is a block diagram of a display device comprising a conventional display address generator, a refresh memory (hereinafter referred to as video memory) in which video data having n bits as a basic unit is stored, and its peripheral devices. Before starting display, the display start address (hereinafter referred to as SAD) of the video memory 1 is sent from the central processing unit (hereinafter referred to as CPU) to the display address counter (hereinafter referred to as SAD) in the display address generator 2 via the system data bus 7.
(hereinafter referred to as DAD) is set to 3.

The display address generator supplies the contents of the DAD to the video memory via the address bus 6 as an output.

Data read from video memory is loaded clock 1
0 is loaded into the parallel-to-serial conversion shift register 4, and the shift clock 11 sequentially supplies an n-bit video serial signal 12 to the CRT. The address generator counts the addresses from DAD+1 to DAD (increases the contents of DAD by +1), and this content is given to the video memory as the output of the display address generator, and the above operation is repeatedly displayed. Let's do it. In such a conventional display device, the address given to the video memory for horizontal display on a CRT is +
It was counted by 1, and only the contents of consecutive addresses in the video memory could be displayed. However, as the applications of image processing expand, various high-quality displays are required. For example, it is required to display the contents of different video memory areas (A and C) as shown in FIG. 2(a) on the same CRT screen. However, in the refresh memory, there is an area A as shown in FIG.
are set so that area B is continuous. In conventional display devices, in the middle of horizontal display, area A (D
7) It was not possible to output an address to display the contents of area C (% starting address is SAD') which is discontinuous from L/s(SAD+n). Therefore, in order to satisfy the request, it is necessary to change the memory contents so that the contents of areas B and C are completely changed within the corresponding address space so that they can be accessed using the continuous display addresses. However, this is not practical if we only consider the time required to rewrite a wide range of video memory and to manage the data, addresses, etc. of area B whose position was previously determined.

SUMMARY OF THE INVENTION An object of the present invention is to provide a device that can divide and display the contents of discontinuous arbitrary address areas on the same screen without changing the contents of the video memory.

The present invention includes a video memory and an address generator that generates display addresses for sequentially reading data stored in the video memory, and this address generator generates a first address used for normal display operation. It includes a counter and a second address counter that is used by the IC when there is a request for screen division, and the selection of the first address counter or the second address counter is controlled by a part of the data in the video menu. The present invention is characterized in that by controlling the second address counter to start and stop counting, data in the video memory with discontinuous addresses is displayed in the horizontal direction.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, in which a refresh memory 21 is used as a video memory and stores data equivalent to several CRT screens. As shown in Figure 4, the data structure of one address (per address) is as follows: n-bit display data (00) that is actually displayed and a display address counter switching control bit DC that is not used for display.
It consists of n+1 bits of B (hereinafter referred to as DAD control bit). In a drawing cycle in which data in the video memory is rewritten, a drawing address is given to the video memory via the address bus 27, at the same time the read signal 30 is activated, and data 5- in the video memory is output to the data bus 26. After the data is captured and processed by a device that processes image information, the write signal 31 is activated and stored in the video memory. 1. Before starting the display, the SAD is sent from the CPU to the system data bus 28.
The first display address counter (hereinafter referred to as DAD 1) 23 of the display address generator 22 is set via the display address generator 22 . When the display starts, DAD 1 based on SAD
starts counting and gives its contents to the video memory via the address bus as the output of the display address generator.

Of the data read out from the video memory, the n-bit data that is actually read out is processed in parallel by the load clock 32.
It is loaded into the serial conversion shift register 25 and converted into a video serial signal 34 by the shift clock 33! Supplied to DCRT. The remaining 1 bit of video data, namely DA
The D control bit is the display address counter switching control signal (
The DAD control signal (hereinafter referred to as the DAD control signal) 29 is applied to the display address generator. The above operation is repeated to display the display.

6- If a request for split-screen display occurs as shown in FIG.
display address counter (hereinafter referred to as DAD2) 2
The display start address (SAD') in the divided area is set to 4, and at the same time, the DAI) control bit of the data in the video memory located at the boundary of one division is rewritten to 1 in the drawing cycle. For example, in FIG. 2, when displayed, data in area A adjacent to area C in the horizontal direction is rewritten by setting the DAD control bit to 1.

After such an operation, data in which the DAD control bit is 1 is read out in the display cycle. Tsu-! When the IDAD control signal is activated, as shown in FIG.
At the same time, the output of the display address generator thereafter is controlled to be the contents of DAD2.

At this time, counting of DADI continues.

In this way, the display address after reading and displaying data whose DAD control bit is 1 is unrelated to the immediately preceding address, making it possible to display the contents of a discontinuous area. The contents of DAD2 become the output of the display address generator, and while displaying, DAD2 is output again.
When data with the AD control bit set to 1 is read out, or when reading of data to be displayed in the horizontal direction is completed, the output of the display address generator is controlled to be the contents of DADI again, and at the same time the contents of DAD2 are changed to the next line. If the value to start counting when the DAD control bit is 1 in the cycle to be displayed, for example, if the horizontal size of the video memory is N, then the contents of the value will change to SAD'+1 → SAD'') By repeating the operation of stopping the count, the contents of areas with discontinuous addresses can be displayed on the screen.

As explained above, if you want to display the screen by dividing it into left and right sides, you can simply rewrite only the data in the video memory located at the adjacent border so that the DAD control bit is set to 1.
Any video memory area display can be mixed,
Furthermore, the display start address of the divided areas can be directly specified, and a complex and sophisticated display as shown in FIG. 2 can be easily realized.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional example of a display device, and Figure 2 (
a) and (b) are diagrams showing the relationship between the display screen and video memory, respectively, FIG. 3 is a block diagram of a display device in an embodiment of the present invention, and FIG. 4 is a diagram showing data in the video memory in an embodiment of the present invention. The configuration diagram, FIG. 5, is a diagram showing the transition of display addresses in the embodiment of the present invention. 1.22...Video memo 1c 2,22...
...Display address generator, 3...Display address counter, 23...First display address counter, 24...Second display address counter, 4
, 25...Parallel-serial conversion shift register, 5
．． 26...Data path, 6°27...
・Address bus, 7, 28... System-data bus, 8, 30... Read signal, 9.31
...Write signal, 10.32...Load clock, 11;33...Shift clock, 12,34...Video-9=Serial signal, 29 ...Display address counter switching control signal. 10- Ward 3

Claims (1)

[Claims] It has a video memory in which image information is stored, and an address generator that generates addresses for sequentially reading out the information stored in the video memory, and the address generator includes at least a first address counter and a second address. 1. An image processing device comprising: a counter, and selectively controlling the first address counter and the second address counter.