JPS5995709A - Microwave semiconductor device - Google Patents
Microwave semiconductor deviceInfo
- Publication number
- JPS5995709A JPS5995709A JP20572582A JP20572582A JPS5995709A JP S5995709 A JPS5995709 A JP S5995709A JP 20572582 A JP20572582 A JP 20572582A JP 20572582 A JP20572582 A JP 20572582A JP S5995709 A JPS5995709 A JP S5995709A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- bias
- gate
- source
- gaasfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はU 21 A S F’ E ’1”を用いた
マイクIff波半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microphone Iff wave semiconductor device using U 21 A S F' E '1''.
近年、マイクロ波帯において良好な性能を有するnチャ
ンネルGaASF’B’l’が開発され、広く利用され
る様になってきた。nチャンネルG aA SFE ’
1’(以下GaA 3 F E’l’という)は、第1
図(a)の回路図に示す様に、Gak S F ET
5のドレインにチョークlを介し正の電源3からの電圧
が印加され(ドレインバイアス)、ソースは接地され、
ゲートにはチョーク2を介し負の電源lOからの電圧が
印加される(ゲートバイアス)。これらドレインバイア
スおよびゲートバイアスはコンデンサ4により外部に電
圧がかからない様に駆出される。この様に、u;3AB
k”ETのバイアス電圧としては、正電圧、以電圧の両
方の電源を必要とし、回路構成が複雑になるという欠点
を有していた。In recent years, n-channel GaASF'B'l', which has good performance in the microwave band, has been developed and has come to be widely used. n-channel G aA SFE'
1' (hereinafter referred to as GaA 3 F E'l') is the first
As shown in the circuit diagram of figure (a), Gak SF ET
A voltage from the positive power supply 3 is applied to the drain of 5 through the choke 1 (drain bias), and the source is grounded.
A voltage from a negative power supply lO is applied to the gate via the choke 2 (gate bias). These drain bias and gate bias are discharged by a capacitor 4 so that no voltage is applied to the outside. In this way, u;3AB
The k''ET bias voltage requires both a positive voltage power source and a lower voltage power source, which has the drawback of complicating the circuit configuration.
一方@1図(b)に示す様に、GaAsFET 5(7
)ドレインにチョーク1を介して正の電源3からのドレ
インバイアスを印加し、ゲートはチョーク2を介し接地
され、ソースはソース抵抗6を介し接地するバイアス印
加方法がある。しかし、この方法は正のバイアス電圧の
みでよいが、ソースにソース抵抗6が入っているために
損失が大きくなり増幅器としてGaA S F E T
を使用する場合には利得ののみで動作し、損失のないL
rBASF E Tのバイアス供給回路をもつマイクロ
波半導体装置を提供すすることKある。On the other hand, as shown in Figure @1 (b), GaAsFET 5 (7
) There is a bias application method in which a drain bias from a positive power supply 3 is applied to the drain via the choke 1, the gate is grounded via the choke 2, and the source is grounded via the source resistor 6. However, although this method requires only a positive bias voltage, the loss increases because the source resistor 6 is included in the source, and GaAs SFET is used as an amplifier.
When using L, it operates only with gain and has no loss.
It is an object of the present invention to provide a microwave semiconductor device having an rBASFET bias supply circuit.
本発明のマイクロ波半導体装置は、ゲートを接地したけ
aA 3 F E Tと、このi=’ E’1’のドレ
インを所星屯圧によりバイアスする回路と、前記B’
E ’l’のゲートを前記電圧によりバイアスする回路
とを含み構成される。The microwave semiconductor device of the present invention comprises a A 3 F ET whose gate is grounded, a circuit which biases the drain of this i='E'1' by a given pressure, and the B'
and a circuit that biases the gate of E'l' with the voltage.
以下本発明を図面を用いて詳f#に説明する。The present invention will be explained in detail below using the drawings.
第2図は本発明の実施例の回路図である。すなわち、U
aAsl’ET51dチョーク1を介してドレインに正
の電源3からバイアスが印加され、ソースは接地され、
ゲートにチョーク2を介して正の電源7からのバイアス
が印加される。この電源7からのバイアスはG、lAs
1+’ET5のゲートの111員方向の立上り電圧以下
の電圧(約0.7 V以下)が印加される。これ以上の
電圧を印加するとGBA Sk’ E ’l’のゲート
よジソースに電流が流れ、雑音の増加、(iaA3FE
Tの劣化を@ftj。FIG. 2 is a circuit diagram of an embodiment of the present invention. That is, U
aAsl'ET51d A bias is applied to the drain from the positive power supply 3 through the choke 1, and the source is grounded.
A bias from a positive power supply 7 is applied to the gate via a choke 2. The bias from this power supply 7 is G, lAs
A voltage (approximately 0.7 V or less) lower than the rising voltage in the 111-member direction of the gate of 1+'ET5 is applied. If a voltage higher than this is applied, current will flow to the gate and source of GBA Sk' E 'l', increasing noise and (iaA3FE
Deterioration of T @ftj.
第3図は本発明の他の実施例の回路図である。FIG. 3 is a circuit diagram of another embodiment of the present invention.
UaAsFE’l’5のドレインにはチョークlを介し
正′亀源3からドレインバイアスが印加され、ソ−スは
接地され、又ゲートバイアスは正電源3よVプリーダ抵
抗8を介し供給され、チョーク2、ゲート抵抗9を介し
接地される。すなわちゲートには正t#3の電圧が、プ
リーダ抵抗とゲート抵抗の分圧比が印加される。A drain bias is applied to the drain of the UaAsFE'l'5 from the positive voltage source 3 through the choke l, the source is grounded, and the gate bias is supplied from the positive power source 3 through the V leader resistor 8, and the choke 2. Grounded via gate resistor 9. That is, a positive voltage t#3 is applied to the gate, which is the voltage division ratio of the leader resistance and the gate resistance.
以上詳細に説明した様に、本発明によればGBA 3F
ETのバイアスは正電圧のみで供給でき、又ソースに抵
抗を挿入する必要がないためその抵抗による損失もない
。As explained in detail above, according to the present invention, GBA 3F
The ET bias can be supplied with only a positive voltage, and since there is no need to insert a resistor into the source, there is no loss due to the resistor.
なお、このマイクロ波半導体装置は、A級で動作する′
電力増幅器に適し、特に電源を少くしたい民生機器の回
路に適当である。Note that this microwave semiconductor device operates in class A'.
Suitable for power amplifiers, especially for consumer equipment circuits that require less power.
第1図は従来のGBA 5 FE Tのバイアス印加方
法を示す回路図、第2図、第3図は本発明の第1および
第2の実施例の回路図である。
図において、1t2・・・・・・チョーク、3t7・・
・・・・正電源、4・・・・・・コンデンサ、5・・・
・・・GaA3F E’I’、6・・・・・・ソース抵
抗、8・・・・・・プリーダ抵抗、9・・・・・−抵抗
、10・・・・・・負心源、である。FIG. 1 is a circuit diagram showing a conventional bias application method for a GBA 5 FET, and FIGS. 2 and 3 are circuit diagrams of first and second embodiments of the present invention. In the diagram, 1t2...Choke, 3t7...
...Positive power supply, 4...Capacitor, 5...
...GaA3F E'I', 6... Source resistance, 8... Leader resistance, 9... - resistance, 10... Negative center source. .
Claims (1)
’ E Tのドレインを一方の極性の電圧によりバイア
スする回路と、前記l″ETのゲートを前記電圧により
バイアスする回路とを含むマイクロ波半導体装置。G, IA4 k' ET with the source grounded, and this l=
A microwave semiconductor device including a circuit that biases the drain of the 'ET with a voltage of one polarity, and a circuit that biases the gate of the l''ET with the voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20572582A JPS5995709A (en) | 1982-11-24 | 1982-11-24 | Microwave semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20572582A JPS5995709A (en) | 1982-11-24 | 1982-11-24 | Microwave semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5995709A true JPS5995709A (en) | 1984-06-01 |
Family
ID=16511643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20572582A Pending JPS5995709A (en) | 1982-11-24 | 1982-11-24 | Microwave semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5995709A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999033172A1 (en) * | 1997-12-22 | 1999-07-01 | Hitachi, Ltd. | Power amplification system and mobile radio communication terminal |
US6678507B1 (en) | 2000-08-31 | 2004-01-13 | Hitachi, Ltd. | Power amplifier system and mobile communication terminal device |
US6861905B2 (en) | 2000-05-08 | 2005-03-01 | Renesas Technology Corp. | Power amplifier system and mobile communication terminal device |
JP2007135298A (en) * | 2005-11-10 | 2007-05-31 | Terasaki Electric Co Ltd | Electric switchboard |
-
1982
- 1982-11-24 JP JP20572582A patent/JPS5995709A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999033172A1 (en) * | 1997-12-22 | 1999-07-01 | Hitachi, Ltd. | Power amplification system and mobile radio communication terminal |
US6708022B1 (en) | 1997-12-22 | 2004-03-16 | Renesas Technology Corporation | Power amplification system and mobile radio communication terminal |
US6861905B2 (en) | 2000-05-08 | 2005-03-01 | Renesas Technology Corp. | Power amplifier system and mobile communication terminal device |
US6678507B1 (en) | 2000-08-31 | 2004-01-13 | Hitachi, Ltd. | Power amplifier system and mobile communication terminal device |
JP2007135298A (en) * | 2005-11-10 | 2007-05-31 | Terasaki Electric Co Ltd | Electric switchboard |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4518926A (en) | Gate-coupled field-effect transistor pair amplifier | |
JPS5413779A (en) | Semiconductor integrated circuit device | |
CA1115790A (en) | Mos fet amplifier | |
US4336503A (en) | Driver circuit having reduced cross-over distortion | |
JPS5942495B2 (en) | negative resistance circuit | |
JPS5995709A (en) | Microwave semiconductor device | |
EP0618674B1 (en) | Voltage-to-current conversion circuit | |
EP1014567B1 (en) | Improvements in or relating to an operational amplifier | |
JPS59214311A (en) | Integrated circuit device | |
JP3178494B2 (en) | MOSFET power amplifier | |
US4060770A (en) | Differential amplifier | |
JP3341945B2 (en) | Operational amplifier | |
JP3343299B2 (en) | Output circuit | |
JPS607210A (en) | Double balanced mixer device | |
JPH0656940B2 (en) | Logarithmic amplifier circuit | |
JPH03120902A (en) | Semiconductor device and mixer circuit | |
US3875536A (en) | Method for gain control of field-effect transistor | |
JPS5924196Y2 (en) | FET switch circuit | |
JPH09223937A (en) | Amplifier circuit | |
JPS58209212A (en) | Transistor circuit | |
JP2004180015A (en) | Cascode amplifier circuit | |
JPS5819855Y2 (en) | FET amplifier | |
JPH0331084Y2 (en) | ||
JPH032988Y2 (en) | ||
JPS61174806A (en) | Power amplifier |