JPS5985185A - Television receiver - Google Patents

Abstract

PURPOSE:To obtain a picture of high quality without flicker by using at least three lines, controlling and switching the readout at 1/2H period, taking the correlation of two memory contents and displaying two scanning lines adjacent by 1H period. CONSTITUTION:The video signal is read out in a time a 1/2 of one horizontal scanning period (1H), i.e. in a speed double that at write from a line memory 1 and displayed on the line 1 of a screen 10, the data are read out from the line memories 1 and 2 and taken for the correlation and displayed on the line (1-2). Then, the data is read out from the line memory 2 and displayed on the line 2, read out from the line memories 2, 3 for taking the correlation and displayed on the line (2-3). The data is read from the line memory 3 and displayed on the line 3, read out from the line memories 3 and 1 and displayed on the line (3-1) after correlation.

Description

[Detailed description of the invention] Technical field The present invention relates to a television receiving device.

BACKGROUND ART The standard television system in our country uses an interlace scanning method. As shown in Figure 1, a television receiving device (hereinafter abbreviated as "IV J")
The screen consists of 525 lines, solid line 1 and dashed line 2.
One screen (frame) is composed of two coarse screens (fields) shown by . As is well known, one field is repeated every 1/60 seconds, so if you look at the entire screen, there are 60 cycles, and flicker is not noticeable due to the characteristics of human visual perception. However, the visibility for each of the first field 1 and the second field 2 is 1/3
Since it is repeated every 0 seconds, if you look at the details (for example, line by line), flicker becomes noticeable after 30 cycles. This means that if the edges of characters flicker or if the image moves quickly, a rough scan line structure becomes apparent. The recent increase in brightness and size of TV screens has made this flickering even more noticeable.

Additionally, this flickering is particularly noticeable in still images [elephants;
This will become a problem in still image displays that mainly feature text, such as teletext broadcasting and the Capten System, which are scheduled to be put into practical use in the future, as well as in more detailed displays due to an increase in the number of displayed characters.

Conventionally, as a method to improve this jitter, the image content is stored in a frame memory (or field memory) and the image is transmitted at a field frequency (5Qt in the N-173c standard system).
A method has been proposed in which the readout image signal is reconstructed and displayed using (lz). However, storing the image content of one frame or one field requires a large capacity memory (for example, 1.2 Mbits of frame memory for 300 pixels per line, 240 lines, 8 bits per pixel) and is costly. It was also a problem.

OBJECTS OF THE INVENTION A first object of the present invention is to provide a television receiving device that displays flicker-free, high-quality images in current television systems.

The second purpose is to realize a flicker-free, high-definition screen without using a large-capacity memory, that is, at a low cost.

A third purpose is to enable stable flicker-free screen display by applying the present invention to character and graphic displays such as teletext broadcasting and the Capten system, or to displays on data terminals of personal computers.

SUMMARY OF THE INVENTION In a television receiving device that is equipped with high frequency amplification means, intermediate frequency amplification means, and video detection/amplification means and is displayed on a CRT, a line capable of storing video signals output from the detection/amplification means for one horizontal scanning period is provided. At least three storage means are provided. A first changeover switching means for selectively switching to one of the line storage means is provided at a stage before the line storage means, and a video signal read from each of the line storage means at a rear stage of the line storage means; Second switching means is provided for selectively switching between the video signal read out from each of the two line storage means and a correlated video signal obtained by correlation processing, and outputting the signal to the video signal processing means. The first switching means is set to 1 based on the synchronization signal separated from the video signal output from the detection/amplification means.
A switching control means is provided which performs switching control for each horizontal scanning period, and also controls switching of the second switching switching means every horizontal scanning period, and further includes a switching control means for controlling switching of the second switching switching means for each horizontal scanning period, and further includes a switching control means for controlling switching of the second switching switching means for each horizontal scanning period, and further includes a switching control means for controlling switching of the second switching switching means for each horizontal scanning period; A storage control means is provided for controlling at least writing and reading in the line storage means, and the video signal read from the line storage means and the correlated video signal subjected to correlation processing are sequentially displayed as two scanning lines in one horizontal scanning period. Configure. In other words, when there are three line storage means, when a video signal is written to one of the three line storage means, the other two line storage means can be read, and the reading speed is twice that of the writing speed. Then, it is read out from one line storage means, and then read out again from the same line storage means that was read out, and at the same time, read out from another line storage means and subjected to correlation processing. It is characterized by displaying two scanning lines adjacent to each other during the scanning period to achieve a flicker-free, high-definition screen.

Embodiments of the present invention will be described below with reference to FIG. 1nj.

Embodiment FIG. 2 is a diagram showing the principle of a non-interlaced scanning method, which is the gist of the present invention. In FIG. 2(a), there are three line storage means capable of storing one image signal for one horizontal scanning period, that is, line memory 1. Line memory 2. A line memory 3 is shown. FIG. 2(1)) shows the CRT screen 10, showing scanning lines corresponding to the outputs of the respective line memories and their correlated outputs.

FIG. 2(C) shows the approximate read/write timing of each line memory. Reading, writing, and displaying of the line memory is performed by the following procedure.

■1 horizontal scanning period from line memory 1 (1xi-63,
The video signal is read out at a reading time of 5 μs, that is, twice as fast as the reading time, and displayed on line (1) of the screen 1o.

(2) Correlation is obtained by reading from both line memory 1 and line memory 2 (the portion where correlation is taken is indicated by diagonal lines in FIG. 2(C)) and displayed on line (1-2).

While these two lines are being displayed, the line memory 3 is in a writing state.

(2) Next, the data is read from the line memory 2 and displayed on line (2).

(2) Read from line memory 2 and line memory 3, correlate and display on line (2-3).

While these two lines are being displayed, the line memory 1 is in a writing state.

(2) Next, the data is read from the line memory 3 and displayed on line (3).

(2) Read from line memory 3 and line memory 1, correlate and display on line (3-1).

While these two lines are being displayed, the line memory 2 is in a writing state. Writing takes one horizontal scanning period (l l(263.
5 μs).

Next, FIG. 3 shows a block diagram of the main parts of the television receiver according to the embodiment.

The television signal inputted from the antenna 11 is converted into a video signal A, which is collectively shown in block 2, by being high-frequency amplified, intermediate frequency amplified, detected, and amplified by the output circuit 12, and becomes a baseband video signal A. This signal is input to the line memory processing circuit 13, which outputs the memory video signal 1 (under the control of the line memory control/switching circuit 14). The signal is input to the signal processing circuit 15 and subjected to a series of processing such as separation of the luminance signal 2 electrical signals and DC reproduction (such as processing of the well-known luminance 9 color difference signals), and then passed through the mixing/switching circuit 16 to the CR' (2) It is output to the drive circuit 17. The output signal is amplified by the CI ('2) drive circuit 17, drives crt-rIB, and is displayed on the screen 10.

On the other hand, the detected and amplified video signal A is line memory system i.
The signal is input to the wholesale/renovation circuit 14 and also to the synchronization separation circuit 19, and the synchronization separation circuit 19 outputs a composite sync signal (COMP 5YNC) to the line memory control/switching circuit 14. On the other hand, the memory video signal I (is inputted to the playback synchronization separation circuit 21 via the switching circuit 20, and the synchronization signals 1 and 14 are separated.The respective outputs are sent to the oscillation drive circuit 22.
The I-pulse generating circuit 23 is used. (2) Generates a vertical sweep signal of oscillation DOF 4F 6Q11z and supplies it to the deflection yoke 25 (vertical). and [3 in the l pulse generation circuit 23]
15 K. 1. -1z H pulse (including AI''C processing) is generated and supplied to the deflection yoke 25 and the high voltage generation circuit 24.

In conjunction with these circuits, this device is used for digital services other than television signals, such as personal computers, teletext, and captain systems (It, G).
, for processing at the B signal level) are also provided. That is, the terminal 26 is an input terminal for digital services, and the service signal is received by the interface circuit 27 into the device. The service signals from the service interface circuit 27 are sent to the mixed switching circuit 1.
6 and is also applied to the switching circuit 20.

The mixing circuit 16 mixes the video signal and the service signal or switches between them. Here R,
It is processed at the G, Bli level. The switching circuit 20 is a circuit for selectively switching the synchronization signal between the television signal and the service signal. Note that although there are other types of service signals in addition to R, G, and J3, there are also video signals, but only R, G, and B will be explained here.

Furthermore, as will be described later, the output signal I (of the line memory processing circuit 13) has a wide band. Therefore, the video signal processing circuit 15, mixed switching circuit 16, CRT drive circuit 17, and CRT 18 are designed with consideration given to the wide band. Further, as mentioned above, the horizontal oscillation frequency of this device is twice the conventional oscillation frequency (15.7 KH7,), that is, 31.5 Kl-1z.

Next, the line memory processing circuit 13 and line memory control/switching control circuit 14, which form the main part of the present invention, will be explained. Figure 4 shows the configuration of 1. Figure 5 does not show the tights chart.

The three line memos IJ], 2, and 3 indicated by reference numbers 31, 32, and 33 are memories that can store video signals for one horizontal period, and in this example, they are digital memories (MoS).
, IC memory, etc.). i of line memory 30? The iJ stage has line memory 1 (311,
Line memory 2 (321, line memory 3 f331
A switch 34 is provided as a first switching means for selectively switching to one of the two. At the subsequent stage of the line memory 30, a correlation video signal 16 is obtained by correlating the video signals read out from each of the line memories 30 and the video signals read from each of the line memories 1, 2, and 3.
A switch 35 is provided as a second switching means for selectively switching and outputting the system. Above switch 3
4.35 are all constructed from semiconductor circuits.

In addition, the correlation circuit 36 also includes the line memory 1 and the line memory 2.
The correlation circuit 37 is for correlating the contents of line memories 2 and 3, and the correlation circuit 38 is for correlating the contents of line memories 3 and 1. In this example, correlation is a process of taking the average of both contents.The average output of both contents is obtained from each of the correlation circuits 36, 37 and 38.

An A/D converter 39 is connected to the input side of the switch 34.
The detected and amplified composite video signal A is numbered with 3[5c, quantized to 8 bits, and output as a digital signal. On the other hand, D/ is connected to the output side of the switch 35.
An A converter 40 is connected, which converts the 8-bit digital signal to an analog signal at a frequency of 6''sc.

In this example, it is composed of an R-2R ladder circuit. As described above, since the composite video signal stored in the linear memo IJ 30 has a blocking bit number of 8 bits (256 gradations), the highest frequency of the composite video signal is 4.2 M[-1z].
, sampling frequency (A/I) converter 39)
is 3'sc (10,7M)lz, fsC=3
．． 58 MHz: color subcarrier frequency) Therefore, each line memory has a capacity of approximately 551 bits. Three lines have a total of H' 16.5 K bits.

The line memory control/switching control circuit 14 includes a memory control circuit 41 that controls the line memory 30 and a switch 34.
．． A switch control circuit 42 that controls switching of both switches 35 and a clock circuit 43 that supplies a lock to an fFJ meme memory control circuit 41 are included. Clock circuit 43
The video signal A and the composite signal (COMP 5YNC
) [7) In particular, l-1-5YNc includes an fsc regeneration circuit 44 which is manually operated, and this circuit 44 extracts the color burst signal and synchronizes it with fSC (3,58MIIz
) is played. This continuous wave is applied to the subsequent read clock generation port ll' 845, multiplied by six, and outputted to the memory control circuit 41 and the write clock generation circuit 46. The 1-inclusive clock generation circuit 46 divides 6rsc to create 3rsc, which is also output to the memory control circuit 41. The memory open side 1 circuit 41 is
'sc to A/D converter 39 + D /
While outputting to the A converter 40, an address signal for the line memory 30 is created using this clock signal.

The switch control circuit 42 selects Q1-1 based on the composite synchronization signal.
Create a credit card and press the switch 34 (not shown in Figure 5), B.
C,1,,), and give the f4 number of memory system 1f1.
The same signal is also applied to one circuit 41. In addition, the switch 35
E, F, G, II, not shown in Figure 5.
I.

The same signal is applied to the memory control 1111 circuit 41 as well as the signal 1a of (2) is changed to Ij. The memory control circuit 41 is
A write command signal is created in response to the signals B, C, and I), while a read command signal is created in response to the signals Ji and J, and this command signal is sent along with the address signal described in 1) over the address bus. Through each line memory 1.2.
Output 4 to 3.

According to FIG. 5, the video signal q′ for non-interlace
We will explain the generation of . In Fig. 5, (3), (1), +21 are connected to the input video signal.
, (3), +IL(2)... The numbers correspond to the number of the line memory being written, and the numbers above the memory output video signal 1 ( 1-
2) , (21, (2-3) , (31, (3
-1), . . . correspond to the number of the light memory being read.

Now, line memory 3 is in concatenation mode (signal is I-1i).
gh), line memory 1 is first set to read mode and read out, and then line memories 1 and 2 are set to read mode and read out. Since two lines are read during the lH period of the write signal, the read clock is twice the 1q write clock (3 fsc) (6 [sc) as described above. In addition, as shown in the video signal A, the switching gate period of the video signal is from the leading edge of LI-S y n (to the next l
It extends up to the leading edge of l-5sync. This is to prevent switching noise from appearing on the display screen. Also, 5
The 1st output switch is synchronized with the 1st word of the write switch, and the timing of 8■+ is read → J-counting clock (317 μS, 7 counts at 682 power)
It is created by

While the line memory 1 is being read, the switch 35 (FIG. 4) is connected to the line memory IJ 1 (31).

Correlation circuit 3 while reading from line memories 1 and 2
Connected to 6. Next, this time line memory 1 (31+
enters the write mode, and the data is read from line memories 2+32), and then from line memories 2 and 3. At the next step 11-1, the line memory 2 goes into the write mode, and the line memories 3 and 3.1 to n are sold out. The signal read out in this way is a video signal of 11 cycles, as shown in the video signal 1 in FIG. The amplitude levels of the contents of the two line memories are averaged, and the 8-bit signals are added together (shifting 1 bit to L5BllllI).Additional weight is added to the correlation process. There are also other methods.

Furthermore, a method of creating two readout scanning lines twice in succession from the same line memory without performing any particular correlation processing can also be considered as a modification. ■Gude (1-2) in Figure 5
→(1), (2→3)→(21, (3-1)→(3
). In this case, the readout switch 35 does not switch on the correlation circuits 36, 37, and 38, and the 2 I
- connected to each of the line memories continuously for one period.

In addition, in the embodiment described above, the line memory is a digital memory.
Analog memory may also be used. In this case, A
/ 11) Convergence, I) /A converter becomes unnecessary.

Further, in the embodiment, the clock circuit 43 may be configured to multiply [SC] by 3 and then by 2 to create 6 fsc. The sampling clock may be generated from a completely independent clock generation source other than one synchronized with the color subcarrier as in this embodiment.

Furthermore, although the above embodiment was based on the Nl'SC method, the technology disclosed herein is of course the l'AL method.

It can be similarly applied to SF and CAM systems.

Effects As described above, the present invention uses at least three line memories to switch and control readout in %H cycles, and to correlate the contents of two memories to display two adjacent scanning lines in III cycles. With this structure, it is possible to display twice as many lines in one field (1/60 seconds) as before, and a high-quality image without flicker can be obtained. Furthermore, there is an advantage that the cost is low because it can be configured with an extremely small capacity memory without using a large capacity field memory or frame memory.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the interlaced scanning method, Figure 2 (a
), (b), and (C) are diagrams for explaining the present invention in detail, FIG. 3 is a block diagram of the main part of the embodiment of the present invention,
FIG. 4 is a detailed block diagram of the line memory processing circuit and line memory open side 1 switching control circuit, and FIG. 5 is a timing chart. 3], , 32, 33... line memory, 34
．． 35...Switch, 36.37.38...Correlation circuit, 41...Memory control circuit, 42...Switch switching control circuit, A...Video signal output from detection/amplification means, 1 (...Video signal based on line memory readout.

Claims (2)

[Claims] (1) At least three line storage means capable of storing the video signal output from the detection/amplification means for one horizontal scanning period are provided, and one of the line storage means is selectively stored in the preceding stage of the line storage means. a first switching means for switching; a video signal read from each of the line storage means;
A second device that selectively switches between the video signal read out from the video signal and the correlated video signal subjected to the correlation processing, and outputs the resultant signal to the video signal processing means.
and the first switching means are controlled to switch every horizontal scanning period based on a synchronization signal that is outputted from the video signal output from the detection/amplification means, and r) o
I. A switching leg means for switching and controlling the second switching means for each horizontal scanning period; and a storage control means for controlling at least writing and reading of the line storage means in accordance with a signal from the switching switching control means. A television receiving device characterized in that the video signal read from the line storage means and the correlated video signal subjected to correlation processing are sequentially displayed as two scanning lines during one horizontal scanning period. . (2) The television receiving device is further provided with an input terminal P for digital services such as teletext and captain system, and has an interface circuit for receiving and receiving service signals, and the service signals and the service signals from the interface circuit. A mixing switching circuit for mixing the video signal or switching to either one, and a same signal switching circuit for switching a synchronization signal between the service signal and the video signal are provided, and the digital service such as double-density teletext is provided. A television receiving apparatus according to claim 1, which is capable of displaying high definition images. ,