JPS5951589A - Printed board - Google Patents
Printed boardInfo
- Publication number
- JPS5951589A JPS5951589A JP14836383A JP14836383A JPS5951589A JP S5951589 A JPS5951589 A JP S5951589A JP 14836383 A JP14836383 A JP 14836383A JP 14836383 A JP14836383 A JP 14836383A JP S5951589 A JPS5951589 A JP S5951589A
- Authority
- JP
- Japan
- Prior art keywords
- coating layer
- land
- solder adhesion
- adhesion prevention
- prevention coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は不透明な絶縁基板の上に銅箔による導電体パタ
ーンを印刷して回路網を形成してなるプリント基板に関
するもので、絶縁基板の裏側に取り付けた電子部器の取
付方向を導電体パターンを印刷する表側からも簡単に識
別することができる構造を提供することを目げとする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printed circuit board formed by printing a conductor pattern made of copper foil on an opaque insulating substrate to form a circuit network. The objective is to provide a structure in which the mounting direction of the conductor pattern can be easily identified even from the front side on which the conductor pattern is printed.
以下１本発明をその実施例を示す図面にもとづいて説明
する。第１図、第２図において、１はプリント基板を構
成する不透明な絶縁基板で、この絶縁基板１の裏側には
、多数のピンを有する１、Ｃ２や抵抗器３等が取り付け
られるが、絶縁基板１にはこれらの電子部品を取り付け
るために一前記工、Ｃ２のリード部４や抵抗器３のリー
ド部６が挿入される孔６，７をそれぞれ設けている。８
は前記１．Ｃ２の取付方向を指示するための切欠き部で
ある。また絶縁基板１の表側には、第２図に示すように
、銅箔による導電体パターン９を印刷して回路網を形成
しており、かつこの導電体パターン９の上には半田付け
するランド１０．１０ａｉ残して絶縁基板１の全体に第
１の半田付着防止塗膜層１１を形成している。さらに半
田付けするランド１ｏの間隔の狭小な部分を有する区域
においては、第１の半田付着防止塗膜層１１とは色の異
なる第２の半田付着防止塗膜層１２が一前記ランド１ｏ
および前記Ｉ、０２の切欠き８と略対応する位置に設け
た電子部品の取付方向識別用ランド１３を残して第１の
半田付着防止塗膜層１１の上に形成されている。The present invention will be explained below based on drawings showing embodiments thereof. In Figures 1 and 2, reference numeral 1 is an opaque insulating board that constitutes a printed circuit board. On the back side of this insulating board 1, 1 having many pins, C2, a resistor 3, etc. are attached. The substrate 1 is provided with holes 6 and 7 into which the lead portions 4 of C2 and the lead portions 6 of the resistor 3 are inserted, respectively. 8
1 above. This is a notch for indicating the mounting direction of C2. Further, as shown in FIG. 2, on the front side of the insulating substrate 1, a conductor pattern 9 made of copper foil is printed to form a circuit network, and on top of this conductor pattern 9 is a land to be soldered. 10. The first anti-solder adhesion coating layer 11 is formed on the entire insulating substrate 1, leaving 10 ai. Further, in an area where the spacing between the lands 1o to be soldered is narrow, a second solder adhesion prevention coating layer 11 having a different color from the first solder adhesion prevention coating layer 11 is applied to the land 1o.
It is formed on the first solder adhesion prevention coating layer 11, leaving behind a land 13 for identifying the mounting direction of the electronic component, which is provided at a position substantially corresponding to the notch 8 of I, 02.
上記したように、第１の半田付着防止塗膜層１１とは色
の異なる第２の半田付着防止塗膜層１２全。As described above, the second anti-solder adhesion coating layer 12 has a different color from the first anti-solder adhesion coating layer 11.
ランド１０および電子部品の取付方向識別用ランド１３
を残して第１の半田付着防止塗膜層１１の上に形成する
ことにより、絶縁基鈑１の裏側に取り付けた多数のピン
を有する１、０２のピンを絶縁基板１の表側から数える
場合等、電子部品の取付方向識別用ランド１３が同一面
内にあるため、絶縁基板１をいちいち裏返して見る必要
はなくなり。Land 10 and land 13 for identifying mounting direction of electronic components
When counting pins 1 and 02 having a large number of pins attached to the back side of the insulating board 1 from the front side of the insulating board 1, etc. Since the lands 13 for identifying the mounting direction of electronic components are on the same plane, there is no need to turn over the insulating substrate 1 to view it.
非常に便利である。また電子部品の取付方向識別用ラン
ド１３には第１の半田付着防止塗膜層１１が形成されて
いるため、絶縁基板１のディップ時に半田層が形成され
ることはなく、絶縁性能等の問題はなくなる。Very convenient. In addition, since the first solder adhesion prevention coating layer 11 is formed on the land 13 for identifying the mounting direction of the electronic component, a solder layer is not formed when the insulating substrate 1 is dipped, which causes problems such as insulation performance. will disappear.
以上のように本発明によれは、絶縁基板の導電体パター
ンを印刷する而に一半田付けするランドを残して全体に
第１の半田付着防止塗膜層を形成するとともに、前記ラ
ンドの間隔の狭小な部分をする区域においては、この区
域における半田付はランドおよび電子部品の取付方向識
別用ランドを残して第２の半田付着防止塗膜層を第１の
半田付着防止塗膜層の上に形成したもので、電子部品の
取付方向識別用ランドが絶縁基鈑の表側に露出した状態
となるため、絶縁基板の裏側に取り付けた電子部品の取
付方向は、絶縁基板をいちいち裏返すことなく、絶縁基
板の表側から簡単に識別することができるという利点を
有するものである。As described above, according to the present invention, when printing a conductor pattern on an insulating substrate, a first solder adhesion prevention coating layer is formed on the entire surface, leaving one land to be soldered, and the spacing between the lands is adjusted. When soldering in a narrow area, the second solder adhesion prevention coating layer is placed on top of the first solder adhesion prevention coating layer, leaving a land for soldering in this area and a land for identifying the mounting direction of the electronic component. Since the lands for identifying the mounting direction of electronic components are exposed on the front side of the insulating board, the mounting direction of electronic components mounted on the back side of the insulating board can be determined without turning over the insulating board one by one. This has the advantage that it can be easily identified from the front side of the substrate.
第１図は本発明の一実施世」を示すプリント基板に電子
部品を取り付けた状態を示す図−第２図は同プリント基
板を導電体パターン側よシ見た図である。
１・−・・・絶縁基板、２・・・・・・Ｉｊｌ、９・・
・・・・導電体パターン−１０，１０ａ・・・・・・ラ
ンｌ−’−１１・・・・・・第１の半田付着防止塗膜層
、１２・・・・・・第２の半田付着防止塗膜層、１３・
・・・・・電子部品の取付方向識別用ランド。FIG. 1 is a diagram showing a state in which electronic components are attached to a printed circuit board showing one embodiment of the present invention, and FIG. 2 is a diagram of the same printed circuit board viewed from the conductor pattern side. 1...Insulating substrate, 2...Ijl, 9...
... Conductor pattern -10, 10a ... Run l-'-11 ... First solder adhesion prevention coating layer, 12 ... Second solder Anti-adhesion coating layer, 13.
...Land for identifying the mounting direction of electronic components.
Claims (1)
刷して回路網を形成してなるプリント基板において、前
記絶縁基板の導電体パターンを印刷する面に、半田付け
するランドを残して全体に第１の半田付着防止塗膜層を
形成するとともに、前記ランドの間隔の狭小な部分を有
する区域においてに−この区域における半田付はランド
および電子部品の取付方向識別用ランドを残して第２の
半田付着防止塗膜層を第１の半田付着防止塗膜層の上に
形成したプリント基板。In a printed circuit board in which a circuit network is formed by printing a conductor pattern made of copper foil on an opaque insulating substrate, the surface of the insulating substrate on which the conductor pattern is printed is entirely covered with a land to be soldered. While forming the first solder adhesion prevention coating layer, in the area where the land spacing is narrow - soldering in this area leaves the land and the land for identifying the mounting direction of the electronic component, and the second solder adhesion prevention coating layer is formed. A printed circuit board having a solder adhesion prevention coating layer formed on a first solder adhesion prevention coating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14836383A JPS5951589A (en) | 1983-08-12 | 1983-08-12 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14836383A JPS5951589A (en) | 1983-08-12 | 1983-08-12 | Printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5951589A true JPS5951589A (en) | 1984-03-26 |
Family
ID=15451085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14836383A Pending JPS5951589A (en) | 1983-08-12 | 1983-08-12 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5951589A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62121732U (en) * | 1986-01-25 | 1987-08-01 | ||
| JPH01161368U (en) * | 1988-04-27 | 1989-11-09 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4319740Y1 (en) * | 1965-08-31 | 1968-08-17 |
-
1983
- 1983-08-12 JP JP14836383A patent/JPS5951589A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4319740Y1 (en) * | 1965-08-31 | 1968-08-17 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62121732U (en) * | 1986-01-25 | 1987-08-01 | ||
| JPH0514418Y2 (en) * | 1986-01-25 | 1993-04-16 | ||
| JPH01161368U (en) * | 1988-04-27 | 1989-11-09 |
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