JPS5944831A - Deposition of thin film - Google Patents
Deposition of thin filmInfo
- Publication number
- JPS5944831A JPS5944831A JP15470382A JP15470382A JPS5944831A JP S5944831 A JPS5944831 A JP S5944831A JP 15470382 A JP15470382 A JP 15470382A JP 15470382 A JP15470382 A JP 15470382A JP S5944831 A JPS5944831 A JP S5944831A
- Authority
- JP
- Japan
- Prior art keywords
- film
- deposition
- deposited
- resistor pattern
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008021 deposition Effects 0.000 title claims abstract description 10
- 239000010409 thin film Substances 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 229910052736 halogen Inorganic materials 0.000 claims 1
- 150000002367 halogens Chemical class 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000001755 magnetron sputter deposition Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 238000007733 ion plating Methods 0.000 abstract description 2
- 229910000676 Si alloy Inorganic materials 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 11
- 239000010408 film Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- 241000555745 Sciuridae Species 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000003921 oil Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- 241000254032 Acrididae Species 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001278 Sr alloy Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000035784 germination Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- ZFXYFBGIUFBOJW-UHFFFAOYSA-N theophylline Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC=N2 ZFXYFBGIUFBOJW-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
この発明は、薄膜堆積方法に関し′ヒＣに凹凸ある７＋
’−扱、３４而七でのγ；、’Ｊ、 ｌｉへ堆れ１方法
の改良に係わる。[Detailed description of the invention] [Technical field to which the invention pertains] This invention relates to a method for depositing a thin film.
'- Treatment, 34 and 7, γ;, 'J, li 1 Concerning the improvement of the method.
［ｉ１１’、３１′技術とその問題点〕近年ｉｔ％（Ｌ
Ｓ Ｉロジックデバイスには、Ａｅ多層配線技術が必
要とされＣいる。多層配線技術には、層１１１０ｐＨ、
Ｉ！’ｉ’＝ ｌｌｉ卓が必す５゛２ニされる。層間絶
縁脱杭１−５１帽圧が充分大であること、リーク？イ淀
が小であることおよび可動イオンを含まないこと等、絶
、縁１時と１７で本来備えるべき性ηに加えて、堆積中
に１層目のＡｅにヒロックを生じない様、低温で堆稈＋
ｒ”３’ ６１°であること１、・よびステップカバ
レッジが口りｊであることなどの干」三値が要求される
。[i11', 31' technology and its problems] In recent years it% (L
SI logic devices require Ae multilayer wiring technology. Multilayer wiring technology includes layer 1110pH,
I! 'i'=lli table must be 5゛2. Interlayer insulation pile removal 1-51 Check that the cap pressure is sufficiently large, leakage? In addition to the properties η that should be present in the Ae layers 1 and 17, such as having a small Ae stagnation and not containing mobile ions, it is necessary to Culm +
The following three values are required: r"3' is 61 degrees, and the step coverage is 61 degrees.
従来、層間絶縁膜（・」１、スパッタリング法やグラス
Ｙ ＣＶ Ｄ （Ｃｈｅ＋ｎ１ｃａｌ Ｖａｐｏｒ ｒ
）ｅｐｎｓｉｔｉｏｎ ）汐によりバ２成されてきたが
、質的に良好な絶縁膜を形成するだめには、３００°０
以上の基板温用を必９ｊｉとすＺ）１−、ステップカバ
レッジ１は必ずしも１．ｌＪＪでｉ、、１ないという問
題点があった。Conventionally, interlayer insulating films (・'1, sputtering method and glass YCVD (Che+n1cal vapor r
)epnstation) Although the insulation film has been formed by Ushio, in order to form a qualitatively good insulating film, it is necessary to
The above substrate temperature must be 9jiZ) 1-, step coverage 1 is not necessarily 1. There was a problem that there was no i,,1 in lJJ.
本発明は、上記り”１＃点に鮨みてなされたものてちり
、凹凸ある基板表面上に良好なステップカバ１゜ツジで
絶縁膜の堆積を行なうとどを目的とｌ、 ｆいる。The present invention is based on the above-mentioned point 1# and aims to deposit an insulating film on an uneven substrate surface with a good step cover.
本発明は薄１漠の堆ｕｉと准稍しｆｒ、 ＩＩ！Ｊの：
Ｔ−ソブングを同時に進行さぜることを／ｌす徴とジろ
。The present invention is similar to the one described above, II! J's:
T-Sobung should be progressed at the same time.
本発明によればステップカバレッジの良ｔ「な薄ＩＩ（
厚ｌ（１精がｏＪ能である。According to the present invention, step coverage is good.
Thick l (1 essence is oJ ability.
本発明において４−Ｊ１薄膜形成の一手段と１〜でイメ
ンプレーデイング法を採用した。第１図は、本発明で１
４・用し／ｒ、イオンブレーティング装置〜の概略を示
す。ペルジャー１内に、ウエーノ・ステージ２゜ｒｆ放
電用コイル醒極３．ノ・−ス４．宜子銃５を備える。排
気糸は、油回転ポンプ１１とクライオポンプ６から成る
。バリアプルリークパルプ７を介［７でペルジャー１内
に酸素ガスを導入し、１０’’ｒｎ ｒｒ台の圧力下で
、ハース４内のシリコン８を電子ヒームによりＸＩに梵
さぜ、スイッチング回ｙ？ｉ ９を介しでｒｆ ｔＫｉ
）Ｇｉ １ （＋から供給されたｒｆ電力により、蒸発
し７ｊ３ｉと０．を数箱せしめる。８１は０２分子およ
び放電によって発生した酸素ラジカルヤイメンによって
酸化ゴれ、ウエーノ・ステージ２下面に固定されたウェ
ーノル１１上に堆ｆ０する。ｒｆ放電することなく、酸
素分子だけで蒸発したシリコンの酸化は可卵である。こ
の方法を、反応性蒸］楕汐と叶ぶことにする。In the present invention, the Imen plating method was adopted as one means for forming the 4-J1 thin film. FIG.
4. An outline of the ion blating device is shown. Inside the Pelger 1, a Ueno stage 2° RF discharge coil is placed.3. No-s 4. Equipped with Yiko gun 5. The exhaust line consists of an oil rotary pump 11 and a cryopump 6. Oxygen gas is introduced into the perger 1 through the barrier pull leak pulp 7 [7], and under a pressure on the order of 10''rnrr, the silicon 8 in the hearth 4 is heated to ? rf tKi via i9
)Gi 1 (Due to the rf power supplied from +, it is evaporated and several boxes of 7j3i and 0. The oxidation of silicon evaporated by oxygen molecules only without RF discharge is possible.This method will be realized as a reactive evaporation method.
第２図は、１μｍの高さの矩形パターンおよび：３μ所
程度の７１ダの上に約１μｍ７１斤の５ｉ０２股を准１
１°・１．だ２１ハ合の形状を模式的に示しだ図であ２
）。′＋＋Ｊ子ビー広ビーム蒸発源１．２ＫＷ、 Ｏ，
圧力３ Ｘ １０−’ Ｔｏｒｒと１−、た。Figure 2 shows a rectangular pattern with a height of 1 μm and a 5i02 crotch of about 1 μm and 71 loaves on a 71 da of about 3 μm.
1°・1. Figure 2 schematically shows the shape of the joint.
). '++J Bee wide beam evaporation source 1.2KW, O,
The pressure was 3 x 10 Torr and 1 Torr.
（ａ）（ハ反応性蒸着法の場合であり、ステップエツジ
において、オーバーハング形状を呈するっこれｒａｔ
１スパツタリング法や蒸着法において一般的にすｃ−）
れる現象であり、ステップによるシャドインク効堅カ原
因テアル。一方（＋３） ｌｄ、ｒｆ ′（Ｉ力５ （
１（ｌ Ｗのイオンシレーティング法−で１１６ ｆｌ
’ｉ ｔ、だを１台であ２）か、良好な形状を呈する。(a) (C) This is the case of the reactive vapor deposition method, and this rat exhibits an overhang shape at the step edge.
1 Generally in sputtering method and vapor deposition method c-)
This is a phenomenon caused by the shadow ink effect caused by steps. On the other hand (+3) ld, rf ′(I force 5 (
1 (l W ion silating method - 116 fl
'It is possible to obtain a good shape with just one machine.
これ１は放電し一〇ノ′ラスマを発。This 1 discharges and emits 10 no's of lasma.
生じた結果、試料表面にもシースが形成びれ、イメンが
基板に対して乎直に入射し１．唯ｆ／ｌ した）１・、
Ｖの一部をリスバッターしたためシャドイング効果が緩
和式れたものと考えられる。As a result, a sheath is also formed on the sample surface, and the particles are directly incident on the substrate.1. Yui f/l did) 1・,
It is thought that the shadowing effect was alleviated because part of the V was subjected to squirrel batter.
３／１７’ｌ１％を度の溝の場合に１ｒｌ１、；ｉ’ｔ
’ｌ ｌ：ｌ （＋１）のどとくイオンブレーティン
グ法により埋め込むことブベＥ１１ ｒｉｉ’であるが
、１μフルあるいはザフ゛ミクロンの濯３の」甲め込み
は容易ではない。イオンシレーティング法においても、
オーバーハング形状となる。このオーバーハング形状と
なる溝の寸法は、Ｉｆｆ￥ｆｒｔ速度と密接な関係があ
る。第３図は、イオンシレーティング法において、Ｊｌ
ＩＴｎ高さのステップにはさ゛まれた（＋”＃に、１μ
ｍｌ’ｌのＳ ＋０２１ｉ／Ｍを堆積した場合にｒｆ
′ｒｉｇ力５ Ｕ ＯＷ、 （’）ｔ １１−力３ Ｘ
１０−”ｒｏｒｒ ”４子ビーム１．２ＫＷにお０る
メーパーハング形状を呈する溝の寸法と堆積１乗ＦＷの
関係４・示す。たとえ１７．ｌ：１．ｉ１和１！（慮ｐ
ｉ２０００人／分の時、寸法１１ｎｎの溝ではオーバー
ハング形状となり、うまく埋め込めないが、１５０Ｘ、
／分では、０５μｍの溝までオーバーハング形状を示さ
ず埋め込むことが司＃ｉ１′である。この現象（ｌよ、
第２図でも述べたとおり、リスバッターの効〃・で説明
されると考えられる。す／ｒわち、一定ｒｆ電力による
）Ｊ’（ｔｉ℃下で１・ｌ１、圧力か−＞’ｒｌでろ、
ろ限り、発生するイオンｌｊｉ’、 Ｉｆ、１、一定で
あり、リスバッタ−１東度は一定である。3/17'l1% in case of groove of degree 1rl1, ;i't
Although it is possible to embed it using the ion blating method, it is not easy to embed it with 1μ full or 1 μm ion blasting. Also in the ion silating method,
It has an overhang shape. The dimensions of the groove forming this overhang shape are closely related to the If\frt speed. Figure 3 shows Jl in the ion silating method.
ITn height step (+”#, 1μ
rf when depositing ml'l of S+021i/M
'rig force 5 U OW, (')t 11-force 3 X
10-"Relationship 4 between the dimension of a groove exhibiting a mapper hang shape and the first power of deposition FW for a 1.2 KW quadrupling beam is shown. Parable 17. l:1. i1 sum 1! (considered)
At i2000 people/min, a groove with a dimension of 11 nn will have an overhang shape and cannot be filled well, but 150X,
/min, it is necessary to embed the groove up to 05 μm without showing an overhang shape. This phenomenon (l,
As mentioned in Figure 2, this is thought to be explained by the effect of squirrel batter. S/r, that is, due to constant rf power) J' (1·l1 at ti℃, pressure ->'rl,
As long as the ions are constant, the generated ions lji', If, 1 are constant, and the east degree of the squirrel batter 1 is constant.
このリスバッタｉ！ｉ Ｉｎに対して、堆積速度が（止
めて犬である時、ごく少ｈ１のリスバッターでりよシャ
ドイング効果を抑制しきれ外いため、刊−バーハング形
状となる。一方堆ｆｉｔ １ｙｆｉ ＩＱ、が小の時、
リスバッターは充分に作用し、オーバーハング形状を抑
制する。This squirrel grasshopper i! For i In, when the deposition rate is small, the shadowing effect cannot be suppressed by a very small squirrel batter, resulting in a bar hang shape.On the other hand, the deposition rate is small. Time,
The squirrel batter works well and suppresses the overhang shape.
上記結果からの９”、Ｉｉ推として、リスバッターとＩ
’ｉｊ１様な方向性エツチングを強制的に起と干ことに
より、より狭い溝を埋め込むことが用卵であると（ＩＩ
Ｍされる。そこで、系内に０２： ＣＦ４＝ １０ ：
１の１１１１杓でＣＦ４ガス多・導入して第３図と同
様の実験を行なった結芽・を第４図に示す。方向性エツ
チングの動片は明らかである。From the above results, Squirrel Batter and I are recommended as 9” and Ii.
The idea is to embed a narrower groove by forcing directional etching like 'ij1 (II
M is done. Therefore, in the system 02: CF4= 10:
Fig. 4 shows the germination results of an experiment similar to Fig. 3 in which a large amount of CF4 gas was introduced using the 1111 ladle of No. 1. The movement of directional etching is obvious.
以下に本発明の実施例を図面を用いて説、明する。Embodiments of the present invention will be described and explained below using the drawings.
Ｐ型３１基板１２を２０枚を形成する。つづいでマグネ
トロンスパッタ装置により、ｈｅ １ ％ Ｓｒ 合
金膜１４を１μｍ膜Ｊ７で堆積し、ポジ型７メトレジス
ト（東京応化社製ＱＦＰＲ−８００） を９Ｊ・＋１
１シて、１μｍ、 ＋１］のＡｅ配線川用しストパター
ン１５を形成し。20 P-type 31 substrates 12 are formed. Next, using a magnetron sputtering device, a he 1% Sr alloy film 14 was deposited with a thickness of 1 μm J7, and a positive type 7 metresist (QFPR-800 manufactured by Tokyo Ohka Co., Ltd.) was deposited at 9J·+1.
After that, an Ae wiring pattern 15 of 1 μm and +1 was formed.
だ（図５ （ａ） ）。該レジストパターン１５をマヌ
クトシ、ＣＣｌ４／Ｃ１１ｔ （ｍ ｈｔ ２０ｍ（１
’ 、 ＮＩＪｅＪｔ １ ： １ ） ｒ（出力３５
０Ｗの苧件下でＡ（？ ＩＩＭ １．４のエツチングを
行なった後、レジスト膜を除去し７た。ここで２０枚の
Ｓｉ基本を１０枚づつ２和に分け、一方を０！雰囲気で
のイオンブレーティング法（０，圧力３ Ｘ １０ ’
Ｔｏｒｒ１！ｊ ｇ＋１１出力１．２ ＫＷ 、 ｒ
ｆ ７Ｊ力５００Ｗ）で、他方をＯ１／ ＣＦ４ ｒ）
Ｙ負１比１（１：ｌの割合でＣＦ、を含有した雰囲気下
でのイオンフレーティング法で、それぞれ酸化シリコン
膜１６をｆｔｆｉ （Ｊ４ Ｌだ。４７いてマグネトロ
ンスパッタ法により２層目のＡｌ膜１７を堆ｔ／ｌＬ、
１層］１と同様の工、Ｔ′−でパターン形式を行なった
。次にｆＰＪ１層目と同様の条件で２Ｐ目の＾ｅ膜のエ
ツチングを行庁いｈｅ配縮を形成した。（＋））該２層
目のＡ６配線のオープン／ショートテストを行なったと
ころ （Ｎ Ｆｌ、を含まない争件下で層間？縁膜の堆
積を行なつｔ二場合（ｆ」：、Ｉ Ｎ１目のＡＩ！膜エ
ツジ、１−？）Ｉ（Ｋ：位置する２層目のＡｅ配線にメ
ープン不良が多く見られた。(Figure 5(a)). The resist pattern 15 is coated with CCl4/C11t (m ht 20m (1
' , NIJeJt 1 : 1 ) r (output 35
After performing A(? IIM 1.4 etching) under 0W conditions, the resist film was removed and the 20 Si basics were divided into 2 sums of 10 each, and one was etched in a 0! atmosphere. Ion brating method (0, pressure 3 x 10'
Torr1! j g+11 output 1.2 KW, r
f 7J force 500W) and the other O1/CF4 r)
The silicon oxide film 16 was formed by ftfi (J4 L) using an ion plating method in an atmosphere containing CF at a ratio of 1:1, and the second layer of Al was formed by magnetron sputtering. Deposit the membrane 17/lL,
[Layer 1] The same process as in 1 was carried out, and a pattern was formed at T'-. Next, the 2P^e film was etched under the same conditions as for the first fPJ layer to form a he arrangement. (+)) An open/short test was conducted on the A6 wiring in the second layer. Eye AI! Membrane edge, 1-?) I (K: Many maple defects were observed in the located Ae wiring of the second layer.
ｔ１１１図は、本発明で使用したイオンレ“レーティン
グｊ０ ｆ＃ｆの概略を示す図、第２図は、スペースに
よ？ける堆積形状を示す図、第３図及び＄４図は、堆積
速熱゛と埋め込み可能なスペース寸法との関係金示す図
、第５図は、Ａｅ配線のメーグン／ショートテスト用試
料作製二■二程を示す断面図である。
１・・・ペルジャー ２１ウエーハスデージ３・・コ
イル？ＩＨＵ ４・・・ハース５・・・’ｒ眞子Ｑ
フィラメント ６・・クライオボニ・）７・・・バリア
プルリークパルプ ８・・・、９１９・・・マツチン
グ回路 １０・・・ｒｆ電源１１・・油回転ポンプ
１２・・・Ｆ’ｆＦＡＳｉ基版１３・・基部１
３膜 １４・・１層目Ｎｅ ｓ１５・・Ａｌ
配縮用レジストパターン
１６・・・酸化シリコン膜 １７・・・２層目Ａｅ
＋＋＋ａ（７３１７）代理人弁理士 則 近 憲 佑
（＋５．か１名）第 １ 図
第２図
第 ３ 図
ｉｎ；噸ヒ、及 （１〆も〆３）゛ン
第 ４ 図
五播連及（ｉβ）Figure t111 is a diagram showing the outline of the ion rating j0f#f used in the present invention, Figure 2 is a diagram showing the deposition shape depending on the space, Figures 3 and 4 are diagrams showing the deposition rate Figure 5 is a cross-sectional view showing the steps 2 and 2 of preparing a sample for the Ae wiring magnet/short test. 1... Pelger 21 wafer stage 3 ... Coil? IHU 4... Hearth 5...'r Mako Q
Filament 6...Cryobony) 7...Barrier pull leak pulp 8..., 919...Matching circuit 10...RF power source 11...Oil rotary pump 12...F'fFASi base plate 13... base 1
3 films 14...1st layer Ne s15...Al
Resist pattern for shrinkage 16...Silicon oxide film 17...Second layer Ae
+++a (7317) Representative Patent Attorney Kensuke Chika (+5. or 1 person) Figure 1, Figure 2, Figure 3 in; (iβ)
Claims (1)
＜ ｒ’、−がエツチング１１豊８をトまわる東部下で
行々うことをＱ！？徴とする＋ｉす＋ｌＲ堆［【゛１方
法。 （２） ｌ’ｌ／！νｉはスパッタリンク法、蒸着法
またはイオンブレーティング法により行われ、系内に少
Ｍの少ブｃくとも］ １ｆｆｆのハロゲン元素を含有す
るガスがダ゛７人されることを特徴とする特許請求範囲
第１＾ Ｊ）′（ハ’ ｉｌ＋！ ０） ７４１１． ｌ内■情
方法。[Claims] (11 Etching and deposition proceed simultaneously, deposition:, 4
<r', - Q to go under the eastern part of etching 11 Toyo 8! ? Sign +iS +lR [[゛1 method. (2) l'l/! A patent characterized in that ν is performed by a sputter link method, vapor deposition method, or ion blating method, and a gas containing a halogen element of at least 1fff with a small amount of M is introduced into the system. Claim No. 1^ J)'(Ha'il+! 0) 7411. ■Inner way.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15470382A JPS5944831A (en) | 1982-09-07 | 1982-09-07 | Deposition of thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15470382A JPS5944831A (en) | 1982-09-07 | 1982-09-07 | Deposition of thin film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5944831A true JPS5944831A (en) | 1984-03-13 |
Family
ID=15590102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15470382A Pending JPS5944831A (en) | 1982-09-07 | 1982-09-07 | Deposition of thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5944831A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61182219A (en) * | 1985-02-08 | 1986-08-14 | Nippon Telegr & Teleph Corp <Ntt> | Thin film growing method |
| JPS6362238A (en) * | 1986-09-02 | 1988-03-18 | Toshiba Corp | Depositing method of thin film |
| US5112776A (en) * | 1988-11-10 | 1992-05-12 | Applied Materials, Inc. | Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing |
| US5244841A (en) * | 1988-11-10 | 1993-09-14 | Applied Materials, Inc. | Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing |
| JPH07166360A (en) * | 1984-10-25 | 1995-06-27 | Applied Materials Inc | Method for making film adhere from reactive gas plasma on base with small-sized and high density step shape |
| US6087276A (en) * | 1996-10-29 | 2000-07-11 | National Science Council | Method of making a TFT having an ion plated silicon dioxide capping layer |
-
1982
- 1982-09-07 JP JP15470382A patent/JPS5944831A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07166360A (en) * | 1984-10-25 | 1995-06-27 | Applied Materials Inc | Method for making film adhere from reactive gas plasma on base with small-sized and high density step shape |
| JPS61182219A (en) * | 1985-02-08 | 1986-08-14 | Nippon Telegr & Teleph Corp <Ntt> | Thin film growing method |
| JPS6362238A (en) * | 1986-09-02 | 1988-03-18 | Toshiba Corp | Depositing method of thin film |
| US5112776A (en) * | 1988-11-10 | 1992-05-12 | Applied Materials, Inc. | Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing |
| US5244841A (en) * | 1988-11-10 | 1993-09-14 | Applied Materials, Inc. | Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing |
| US6087276A (en) * | 1996-10-29 | 2000-07-11 | National Science Council | Method of making a TFT having an ion plated silicon dioxide capping layer |
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