JPS5936835A - Circuit for forming timing pulse - Google Patents

Abstract

PURPOSE:To form highly accurate various kinds of timing pulses in each data processing part without using an expensive delay element, by distributing a signal electrically superposed information in the period of a main clock pulses to a basic clock pulse. CONSTITUTION:The titled circuit is provided with a means distributing a signal electrically superposed the information in the period of a main clock pulse to a basic clock pulse. For instance, a basic clock circuit 1 creates the basic clock pulse having the prescribed pulse width and a marker circuit 2 creates a distribution clocks obtained by superposing information in the period of main clock pulse whose pulse width is modulated to a basic clock pulse string. The distribution clock is distributed to respective data processing parts 3-1-3-K through transmission lines 28-1-28-K and respective clock separating circuits 4 separate and reproduce the distributed pulse into the main clock pulses and the basic clock pulse. A polypgase clock circuit 5 creates a polyphase clock pulse synchronous with the main clock pulses and various kinds of timing pulses are outputted through an output pulse circuit 6.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a timing pulse generation circuit.

[Prior art]

Conventionally, in a data processing device having a plurality of data processing units that operate in synchronization L7 with one clock signal, two methods have been generally used to create various timing pulses necessary for each data processing unit. There is.

In this method, the main clock pulses are distributed to the main clock processing sections, and various necessary timing pulses are created from the received main clock pulses using mainly delay elements in each data processing section.

This method has a simple configuration and has the advantage of increasing the timing accuracy between each timing pulse within the same data processing unit, but the higher the accuracy, the more expensive delay elements are required. This has the disadvantage that it requires a lot of time, and that it takes a lot of time to adjust the timing, making it expensive.

A second prior art method uses an integer number (N
) Create a basic clock pulse with twice the repetition frequency, and use a counter circuit and a decoder circuit, for example, to generate N multiphase clocks whose phases are shifted one cycle at a time of the basic clock. This is a method in which a pulse is created, this multiphase clock pulse is distributed to each data processing section, and each data processing section uses the distributed multiphase clock pulse to create various timing pulses using set/reset flip-flops, etc. be.

This method has the advantage that relatively accurate timing pulses can be created without using expensive delay elements by increasing the number of phases N of the multiphase clock, but since the distribution is performed using a multiphase clock, This has the disadvantage that the variation in propagation delay time of the transmission line of each phase becomes large, and timing accuracy is limited.

This drawback becomes a big problem when the distribution transmission path length is long. Another disadvantage is that the number of signals to be distributed increases, making connections complicated.

In order to shorten the distribution length, it may be possible to distribute using basic clock pulses instead of using multiphase clocks, and create multiphase clocks and timing pulses in each data processing section, but in this case, Since it is not possible to specify which basic clock pulse each data processing section uses as a reference to create a timing pulse, each data processing section operates asynchronously, and the device as a whole cannot operate normally. there were.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned drawbacks by distributing a signal in which information on the main clock pulse period is electrically superimposed on the basic clock pulse. The purpose of the present invention is to provide a circuit that can be created by a processing unit.

[Structure of the invention]

The circuit of the present invention includes a basic clock circuit that creates a basic clock pulse whose repetition frequency is an integral multiple of the main clock pulse of a data processing device having a plurality of data processing units that operate in synchronization with each other; a marker circuit for outputting a distributed clock in which the amplitude of a pulse corresponding to the period of the main clock pulse in the pulse train is larger than that of other pulses; and a plurality of circuits for distributing the distributed clock to each of the data processing units. The data processing section includes a clock separation circuit that inputs the distributed clock, discriminates the pulse amplitude, separates the main clock pulse and the basic clock pulse, and outputs the separated clock pulses. , inputs the output of the clock separation circuit, synchronizes with the main clock pulse, and outputs one pulse per period of the main clock pulse, and each output is N pulses whose phase is shifted in sequence by one period of the basic clock pulse. The multiphase clock circuit outputs multiphase clock pulses, and an output pulse circuit receives the multiphase clock pulses and generates various timing pulses required by each data processing section.

[Explanation of Examples]

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing a block diagram of an embodiment of the present invention,
The timing pulse generation circuit of the present invention is a basic clock circuit 1 that generates a basic clock pulse whose repetition frequency is an integer (denoted as N) times the main clock pulse of the entire device.
and a marker circuit 2 which inputs the basic clock pulse via the connection point 7 and outputs a distributed clock in which the amplitude of the pulse corresponding to the period of the main clock pulse in the pulse train is larger than the amplitude of other pulses; The distribution clock is transmitted to the transmission lines 28-1 to 28- corresponding to each data processing unit for distributing the distribution clock to a plurality of data processing units 3-1 to 3-K (two units in FIG. 1). The data processing units 3-1 to 3-1 (which create timing pulses from the A clock separation circuit 4 separates and outputs a main clock pulse and a basic clock pulse, and a clock separation circuit 4 inputs the output of the clock separation circuit 4, and outputs one pulse per period of the main clock pulse in synchronization with the main clock pulse. A multiphase clock circuit 5 outputs N multiphase clock pulses whose phases are shifted by one period of the basic clock pulse, and each output outputs N multiphase clock pulses whose phase is shifted by one period of the basic clock pulse. It includes an output pulse circuit 6 that outputs various timing pulses required by the processing units 3-1 to 3- to output terminals 10-1 to 10-M.

The basic clock pulse, which is the output of the basic clock circuit 1, has a repetition frequency N times that of the main clock pulse, which determines the cycle time of the data processing units 3-1 to 3- and the cycle time of the entire device. Since information about the clock pulse cycle is not included, if the basic clock pulse is distributed to each data processing section 3-1 to 3-K, each data processing section 3-1 to 3- will operate in synchronization with each other. It is not possible.

In the present invention, a distribution clock in which main clock pulse synchronization information is superimposed on the basic clock pulse in the amplitude direction is used at marker times M.
2 and distributed to each data processing unit 3-1 to 3-K through each transmission line 28-1 to 28-K. In other words, a distribution clock with increased amplitude is distributed to every N basic clock pulses and clock pulses (7) so as to correspond to the main clock pulse period.The signal level of the distribution clock is 1 novel low, It has three values: the level corresponding to the basic clock pulse, and the highest level obtained by superimposing the basic clock pulse and the main clock pulse.

Inside each data processing section 3-1 to 3-, a clock separation circuit 4 separates the main clock pulse and a basic clock pulse from the received distribution clock, and a multiphase clock circuit 5 separates the main clock pulse and the basic clock pulse from the received distribution clock. 7 output terminals 10-1
~ Output to 10-M.

Each data processing unit 3-1 to 3- separates the main clock pulse from the distribution clock and the main clock pulse and generates various timing pulses that are synchronized with the main clock pulse. Can operate synchronously. Also, considering the timing accuracy of 83 pulses in the data processing section, the periodic accuracy at the output of the basic clock circuit l is almost unrelated to the distribution transmission path length, and Ima ≠
=Yo≠Since it can be stored at least with the output At of circuit 4,
It can create highly accurate output pulses. For example, if a crystal oscillator or the like is used as the oscillation source of the basic clock circuit 1, it is easy to obtain an accuracy of ±0.1% or more for the basic clock oscillation output cycle of the clock separation circuit 4, so the timing pulse output point 10 Even with -1 to 10-M, it is possible to create timing with an accuracy of less than ns. Moreover, it has the great advantage of being inexpensive because it can be done without using expensive delay elements.

Next, an embodiment of the marker circuit 2 according to the present invention will be described in detail with reference to FIG. For simplicity, N is assumed to be 4. In FIG. 2, the marker circuit 2 includes a terminal 7 to which a basic tarlock pulse is input, an inverter circuit 11 whose input is connected to the terminal 7, a quaternary counter circuit 12 whose clock input terminal is connected to the terminal 7, and a counter circuit. A 2-bit decoding circuit 13 which inputs two outputs of 12, and an inno (-
A two-man power AND circuit 14 inputs the output of the input circuit 11 and the output of the decoding circuit 13, a resistor 15 connected between the output of the inno-decoder circuit 11 and the output terminal 8, and the output of the two-man power AND circuit 14. and an output terminal 8, and a terminal 8 that outputs a distributed clock.

FIG. 3 is a time chart for explaining the operation of the marker circuit 2, in which (a) shows the basic clock pulse input to the terminal 7, and (b) shows the contents of the output of the counter circuit 1202 bits (the number of clock pulses counted). ), (C) shows the output of the decoding circuit 13, (d) shows the output of the two-man power AND circuit 14, and (e) shows the distributed clock at the output terminal 8.

Next, the operation will be explained. The basic clock pulse that is the output of basic clock circuit 1 is passed through all terminals 7 to inverter circuit 1.
1 and the clock terminal of the counter circuit 12. The counter circuit 12 is a quaternary counter (Figure 3(b))
As shown in the figure, the contents of the counter repeat four states from 0 to 3. By ANDing the pulse obtained by decoding the 2-bit output of the counter circuit 12 by the decoding circuit 13 and the basic clock pulse whose polarity has been inverted by the inverter circuit 11 in the two-manual AND circuit 14, the result shown in FIG. One basic clock pulse out of every four can be taken out as shown in .The basic clock pulse output from the inverter circuit 11 and the output from the two-man AND circuit 14 are ORed in an analog manner using resistors 15 and 16. By doing this, it is possible to create a distributed clock that includes one out of every four pulses with a large amplitude, as shown in Figure 3(e).The main clock pulse period in the data processing section is four times the basic clock pulse period. Since this case is considered, the distributed clock includes a pulse with a large amplitude of the main clock pulse period and a basic clock pulse.N
can be easily changed by changing the base number of the counter circuit 12.

Next, an embodiment of the clock separation circuit 4, multiphase clock circuit 5, and output pulse circuit 6 in the data processing units 3-1 to 3-3- of the present invention will be described in detail with reference to FIG.

For simplicity, let N be 4 as before. 4th showing the circuit diagram
In the figure, there is a terminal 9 that inputs the distributed clock, a voltage comparator 17 that inputs the distributed clock to the positive phase input and a reference voltage VR,1 to the negative phase input, and a voltage comparator 17 that inputs the distributed clock to the positive phase input and has the negative phase input. A voltage comparator 18 to which the reference voltage V2 is input, a counter circuit 20 which inputs the output of the voltage comparator 17 to the clock input and inputs the output of the voltage comparator 18 to the reset input, and two outputs of the counter circuit 20. Enter 2
The inverter circuit 19 inputs the bit decoding circuit $21 and the output of the voltage comparator 17, and the output of the inverter circuit 19 is inputted to one input, and the output of the decoding circuit 21 is inputted to the other inputs.
Four 2-person AND circuits 2 each inputting the output of the book
2゜23.24.25, the flip-flop circuit 26 which inputs the output of the two-man power AND circuit 22 to the set input and the output of the two-man power AND circuit 24 to the reset input, and the two-man power ANI) circuit 22. A clip-flop circuit 27 which inputs the output to the center and throat inputs and inputs the output of the two-man power ANI) circuit 25 to the reset input, and terminals 10-1 to which the outputs of the flip-flop circuits 26 and 27 are respectively output.
10-2. The circuits surrounded by dotted lines in FIG. 4 correspond to blocks 7 with the same numbers in FIG. 1.

FIG. 5 is a time chart for explaining the 111th work, (a) shows the distribution clock input to terminal 9, (
b), (C) are the outputs of the voltage comparators 17 and 18, (d) is the output of the counter circuit 20, (e) is the first output of the decoding circuit 21, (f), (g), (
h) and (i) are two-manpower AND circuits 22 and 2, respectively.
3.24.25 outputs, (j) and (k>, respectively, represent the output pulses at terminals 10-1.1.0-2.

Next, the operation will be explained. The distributed clock input from terminal 9 is input to the positive phase input of voltage comparators 17 and 18. Since the reference phase voltage V Ri is set to a low level as shown in FIG. 5(a), the voltage comparator 17 reproduces the basic clock signal as shown in FIG. 5(b), and the reference voltage 1 (・21
4, the voltage comparator 18 reproduces the main black and ν pulses as shown in FIG. 5(C).

Since the regenerated main clock pulse is input to the reset input of the counter circuit 20, the counter circuit 20 is reset every time the main clock pulse is input. Therefore, the counter circuit 20 operates as a quaternary counter starting from the input of the main clock pulse as shown in FIG. 5(d).

The 2-bit output of the counter circuit 20 is decoded by the decoding circuit 21.
By ANDing the output decoded by the output and the signal obtained by inverting the polarity of the reproduced basic clock signal by the inverter circuit 19 using the two-man AND circuits 22 to 25, the signals shown in FIGS. ) can create a four-phase multiphase clock as shown in ().

The phase difference between these multiphase clocks becomes the period of the basic clock pulse itself, and its accuracy #1 is the accuracy of the output of the basic clock circuit 1 plus the variation in the delay time of the two-manual AND circuits 22 to 25. be equal. For the output pulse, a multiphase clock that transitions at a point closest to the required timing may be selected and input to the flip-flop circuits 26 and 27. The pulses output from terminal 1O-IK use the outputs of two-man AND circuits 22 and 24, and the output from terminal 10-2
The pulses output to the two human-powered A N D circuits 22 and 25
It uses the output of In this example, K is used for simplicity.
Although N is set to 4, more detailed timing can be created by increasing N.

Furthermore, in order to output N multiphase clocks by the multiphase clock circuit 5, N(N-x) output pulses can be obtained by combining N timings, including polarity. This is an advantage that cannot be obtained by using a delay element to generate timing pulses from the main clock pulse.

In this way, since this circuit can be constructed entirely of digital circuits and resistors, it is suitable for integration.

〔Effect of the invention〕

As described above, the present invention has the advantage that each data processing section operates synchronously and that highly accurate output timing pulses can be easily created without using expensive delay elements.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the marker circuit 2 shown in FIG.
3 is a time chart for explaining the operation of the circuit shown in FIG. 2, FIG. 4 is a circuit diagram showing an embodiment of the data processing section shown in FIG. 1, and FIG. 1 is a time chart for explaining the operation of the circuit shown in FIG. 1...Basic clock circuit, 2...Marker circuit, 3-1 to 3-K...Data processing section, 4
... Clock separation circuit, 5 ... Multiphase clock circuit, 6 ... Output pulse circuit, 7.8-
1 to 8-, 9-1 to 9-K... connection point, 10
-1~10-K...Terminal, 11°19...
...Inverter circuit, 12.20...Counter circuit, 13.21...Decode circuit, 14,2
2～25・・・Two-man power AND circuit, 15.16・
...Resistance, 17.18...°...Voltage comparator,
26.27°°°°°. Flip-flop circuit, 28-1~2 s-to-°°
“°°Transmission line. Flower 22- Concave #3 Figure #4 Concave

Claims (1)

[Claims] A basic clock circuit that creates a basic clock pulse whose repetition frequency is an integer multiple of the main clock pulse of a data processing device having a plurality of data processing units that operate in cycles with each other; a marker circuit for outputting a distribution clock in which the amplitude of a pulse corresponding to the period of the main clock pulse is larger than that of other pulses; a plurality of transmission lines for distributing the distribution clock to each of the data processing units; a clock separation circuit which inputs the distributed clock, discriminates the pulse amplitude, separates the main clock pulse and the basic clock pulse, and outputs the separated clock pulses; and the clock separation circuit. inputs the output of the basic clock pulse, outputs one pulse in the main clock pulse period in synchronization with the main clock pulse, and each output has N multiphase clock pulses whose phase is sequentially shifted by one period of the basic clock pulse. 1. A timing pulse generation circuit comprising: a multiphase clock circuit that outputs the multiphase clock pulse; and an output pulse circuit that receives the multiphase clock pulse and generates various timing pulses required by each of the data processing units.