JPS5933847A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5933847A JPS5933847A JP14440482A JP14440482A JPS5933847A JP S5933847 A JPS5933847 A JP S5933847A JP 14440482 A JP14440482 A JP 14440482A JP 14440482 A JP14440482 A JP 14440482A JP S5933847 A JPS5933847 A JP S5933847A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- forming
- semiconductor
- oxide film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体素子を配列してなる半導体装置の製
造方法、特に素子間分離法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device formed by arranging semiconductor elements, and particularly to a method for separating elements.
従来この種の半導体装置における素子間分離は、一般に
選択酸化技術によって行なわれていた。Conventionally, isolation between elements in this type of semiconductor device has generally been performed by selective oxidation technology.
しかしながら、この方法による場合、バーズビークと呼
ばれる酸化膜の活性領域内へのくい込み、およびバーズ
ヘッドと呼ばれる酸化膜周縁部の盛り上がりによる凹凸
が必然的に生じ、前者は半導体装置の高密度集積化に対
する制約となると共に、後者は高密度集積化に伴う多層
配線技術にとって不都合となっていた。However, when using this method, the oxide film sinks into the active region, called a bird's beak, and the unevenness, called a bird's head, arises due to the swelling of the periphery of the oxide film.The former is a constraint on high-density integration of semiconductor devices. At the same time, the latter has become inconvenient for multilayer wiring technology that accompanies high-density integration.
この発明はこのような状況に鑑みてなされたもので、そ
の目的は、半導体素子からなる半導体装置の平坦性を向
上させ、より高密度な集積化を可能にする半導体装置の
製造方法を提供することにある。The present invention was made in view of the above circumstances, and its purpose is to provide a method for manufacturing a semiconductor device that improves the flatness of a semiconductor device made of semiconductor elements and enables higher-density integration. There is a particular thing.
このような目的を達成するために、この発明は、基板上
に形成した絶縁膜を選択的に除去し、除去部分に減圧下
でのエピタキシャル成長技術により半導体層を形成し、
ここに各半導体素子を形成するものである。In order to achieve such an object, the present invention selectively removes an insulating film formed on a substrate, forms a semiconductor layer on the removed portion by epitaxial growth technology under reduced pressure,
Each semiconductor element is formed here.
即ち、減圧下での選択エピタキシャル成長技術を用いて
活性領域を形成すると共に素子間分離を完成するもので
あり、バーズビーク、バーズヘッドを伴う選択酸化法を
用いず、捷た、従来の常圧(760torr)下で行な
うシリコンの選択エピタキシャル成長技術ではシリコン
島周辺部の異常成長によって中心部に比べて周辺部の膜
厚が大きくなり、この傾向を低減するには種々の成長条
件を厳しく制御する必要があったのに対し、減圧下での
選択エピタキシャル成長技術を用いることにより容易に
上記周辺部での盛り上がりを抑制することを可能にした
ものである。That is, selective epitaxial growth technology under reduced pressure is used to form the active region and to complete the isolation between elements, and instead of using the selective oxidation method that involves bird's beaks and bird's heads, conventional normal pressure (760 torr) growth technology is used. ) In the selective epitaxial growth technique for silicon performed below, abnormal growth at the periphery of the silicon island results in a film thicker at the periphery than at the center, and it is necessary to strictly control various growth conditions to reduce this tendency. However, by using a selective epitaxial growth technique under reduced pressure, it has become possible to easily suppress the swelling in the peripheral area.
減圧下で、例えばジクロルシラン5IH1lCZ21
トリクロルシランSi HCL8+四塩化ケイ素S s
C4というようなシリコン源となるガスを水素をキャ
リーガスとして熱分解して行なうエピタキシャル成長技
術を用いて、あるいは減圧下で上記シリコン源となるガ
スもしくはモノシランガスS iH4と共に塩化水素ガ
スHC1を水素をキャリーガスとして熱分解して行なう
エピタキシャル成長技術を用いて、酸化膜(Si02)
あるいは窒化膜(s t 8N4 )というような
絶縁膜をマスクとしてその開口部にシリコンエピタキシ
ャル層を成長させることにより、従来の厳しく制御され
た常圧下での選択エピタキシャル成長技術に比較して容
易に選択性(酸化膜あるいは窒化膜にポリシリコンが成
長しないこと)および平坦性に優れた選択エピタキシャ
ル成長層を形成できることが確認された。また、素子間
分離膜としての絶縁膜は、選択酸化法を用いず、全面に
形成した絶縁膜に写真食刻法等により開口部を設けるこ
とによって形成するため、バーズビ〜り。Under reduced pressure, e.g. dichlorosilane 5IH11CZ21
Trichlorosilane Si HCL8+Silicon tetrachloride S s
Using an epitaxial growth technique in which a silicon source gas such as C4 is pyrolyzed with hydrogen as a carrier gas, or hydrogen chloride gas HC1 is used together with the silicon source gas or monosilane gas SiH4 under reduced pressure and hydrogen is used as a carrier gas. Oxide film (Si02) is grown using epitaxial growth technology that is thermally decomposed as
Alternatively, by growing a silicon epitaxial layer in the opening using an insulating film such as a nitride film (st8N4) as a mask, it is easier to achieve selective growth compared to the conventional selective epitaxial growth technique under tightly controlled atmospheric pressure. It was confirmed that (polysilicon does not grow on the oxide film or nitride film) and that a selective epitaxial growth layer with excellent flatness can be formed. In addition, the insulating film as the element isolation film is formed by forming openings by photolithography or the like in the insulating film formed over the entire surface, without using selective oxidation, so that the insulating film has a bird's-eye view.
バーズヘッド等の生じる余地はない。There is no room for birds' heads to form.
第1図に、ジクロルシランをシリコン源にすると共にキ
ャリーガスとして水素を用い、1080℃で酸化膜をマ
スクとして得られた選択エピタキシャル層の平坦性の圧
力依存性の一例を示す。平坦性は、第2図において基板
(1)の上に設けられた酸化膜(2)の開口部に形成さ
れたシリコン層(3)の周辺部の厚さAに対する中央部
の厚さBの比で表わした。FIG. 1 shows an example of the pressure dependence of the flatness of a selective epitaxial layer obtained using dichlorosilane as a silicon source and hydrogen as a carrier gas at 1080° C. using an oxide film as a mask. Flatness is determined by the thickness B at the center of the silicon layer (3) formed in the opening of the oxide film (2) provided on the substrate (1) with respect to the thickness A at the periphery in FIG. Expressed as a ratio.
第1図から、減圧下、特に80torr以下での選択エ
ピタキシャル成長によって平坦性を容易に、かつ飛躍的
に向上させることができることが分る。It can be seen from FIG. 1 that the flatness can be easily and dramatically improved by selective epitaxial growth under reduced pressure, particularly at 80 torr or less.
このように向上する理由としては、キャリーガス濃度、
シリコンソースガス(例えばジクロルシラン)および温
度等の諸条件を同じにした場合、減圧下でエピタキシャ
ル成長を行なうと、常圧下に比べて成長速度が遅くなる
こと(4Qtorrで約2制減)およびシリコン基板表
面でのシリコン原子の平均自由工程が長くなること(4
Q torrで約19倍)による影響が考えられる。The reason for this improvement is the carry gas concentration,
When conditions such as silicon source gas (e.g. dichlorosilane) and temperature are kept the same, when epitaxial growth is performed under reduced pressure, the growth rate is slower than that under normal pressure (approx. 2% reduction at 4Qtorr) and the silicon substrate surface The mean free path of silicon atoms becomes longer (4
This is thought to be due to the effect of Q torr (approximately 19 times).
次に、NチャネルMO8型半導体装置を形成する場合の
一実施例につき、図面を用いて説明する。Next, an example of forming an N-channel MO8 type semiconductor device will be described with reference to the drawings.
先ず、第3図に示すようにP形シリコン基板(11)の
表層部(lla)に素子間分離膜下のチャネルドープと
してイオン注入によりホウ素を導入した後、熱酸化によ
り、素子間分離絶縁膜となる酸化膜(J2)を形成する
。次に、写真製版技術およびエツチング技術により活性
領域、即ちMO8型半導体(5)
素子の形成部分となるべき所定の位置の酸化膜(12)
を選択的に除去し、開口部を形成する。次いで、この開
口部に減圧下(この実施例においては4Qtorr)で
エピタキシャル成長を行なうことにより、平坦なエピタ
キシャル層(13)が形成できる。First, as shown in FIG. 3, boron is introduced into the surface layer (lla) of the P-type silicon substrate (11) as a channel dope under the element isolation film by ion implantation, and then the element isolation insulating film is formed by thermal oxidation. An oxide film (J2) is formed. Next, photolithography and etching techniques are used to form the active region, that is, the MO8 type semiconductor (5).
is selectively removed to form an opening. Next, epitaxial growth is performed in this opening under reduced pressure (4 Qtorr in this example), thereby forming a flat epitaxial layer (13).
引続きこのエピタキシャル層(13)に通常の方法によ
りNチャネルMO8型半導体素子を形成することにより
、第4図に示すような半導体装置が得られる。即ち、第
4図において、(14) 、 (1,5)は1拡散層か
らなるソースおよびドレイン、(16)はゲート(17
)はアルミニウムからなる電極、(18)はコンタクト
拡散領域、また(19)は層間絶縁用の酸化膜であり、
(19a)はゲート酸化膜である。Subsequently, by forming an N-channel MO8 type semiconductor element on this epitaxial layer (13) by a conventional method, a semiconductor device as shown in FIG. 4 is obtained. That is, in FIG. 4, (14) and (1,5) are the source and drain consisting of one diffusion layer, and (16) is the gate (17).
) is an electrode made of aluminum, (18) is a contact diffusion region, and (19) is an oxide film for interlayer insulation,
(19a) is a gate oxide film.
なお、上述した実施例においては、酸化膜(12)の形
成方法としてP型シリコン基板(11)の表面を熱酸化
する方法を用いたが、これは他の方法、例えば基板(1
1)の上にポリシリコン層を形成した後にこれを全部酸
化するという方法、あるいはCVD法等により堆積させ
る方法などによってもよい。In addition, in the above-mentioned example, a method of thermally oxidizing the surface of the P-type silicon substrate (11) was used as a method of forming the oxide film (12), but this is not possible using other methods, such as forming the oxide film (12).
A method of forming a polysilicon layer on 1) and then oxidizing it entirely, or a method of depositing it by CVD or the like may be used.
更に、素子間分離膜としては、酸化膜に限らす例えばC
VD法等により形成した窒化膜など他の絶縁膜を用いて
もよい。Furthermore, the isolation film between elements is limited to an oxide film, for example, C.
Other insulating films such as a nitride film formed by a VD method or the like may also be used.
なお、基板(11)へのホウ素の導入は、基板形成工程
で自然にできる表面の薄い酸化膜を通して行なってもよ
いし、この酸化膜を除去して直接イオン注入して行なっ
てもよい。Note that boron may be introduced into the substrate (11) through a thin oxide film on the surface that is naturally formed during the substrate forming process, or by removing this oxide film and directly implanting ions.
また、上述した実施例においては、NチャネルMO8型
半導体素子からなる半導体装置を製造する場合について
のみ説明したが、この発明はこれに限定されるものでは
なく、導電型を逆にしたPチャネルMO8型半導体素子
からなる半導体装置の製造に適用しても同様に有効であ
ることは言うまでもない。Further, in the above-described embodiments, only the case of manufacturing a semiconductor device made of an N-channel MO8 type semiconductor element has been described, but the present invention is not limited to this, and the P-channel MO8 type semiconductor element having the reverse conductivity type is manufactured. It goes without saying that the present invention is equally effective when applied to the manufacture of semiconductor devices made of type semiconductor elements.
更に、例えば固体撮像装置であれば受光素子を配列した
中央部を除くチップ周辺部のように、当該半導体装置の
本来の機能に関与しない部分についても、上述したよう
な減圧下での選択エピタキシャル成長技術を適用するこ
とにより、あるいは更にそれによって形成されたエピタ
キシャル層に上記本来の機能に関与する以外の周辺的な
領域、例えばモニタートランジスタあるいは各種の耐圧
。Furthermore, in the case of a solid-state imaging device, for example, the selective epitaxial growth technique under reduced pressure can be applied to parts that are not involved in the original function of the semiconductor device, such as the peripheral part of the chip excluding the central part where the light receiving elements are arranged. By applying this, or furthermore, peripheral regions other than those involved in the above-mentioned original functions are formed in the epitaxial layer formed thereby, such as a monitor transistor or various breakdown voltages.
導通テスト等のモニターを行なうパターンを形成する領
域を設けることにより、減圧下での選択エピタキシャル
層形成部分の平坦性および選択性を更に向上させ、装置
の品質を高めることができる。By providing a region for forming a pattern for monitoring continuity tests, etc., it is possible to further improve the flatness and selectivity of the selective epitaxial layer forming portion under reduced pressure, and to improve the quality of the device.
つまり、酸化シリコン膜をマスク材料としたシリコン選
択エピタキシャル成長にあっては、シリコンと酸化シリ
コンとの面積比(8i/S1o、)によって、選択性お
よび平坦性が影響を受け、Si//5io2ノ面積比を
大きくすることにより選択性および平坦性は向上するの
で、本来の半導体装置以外の部分にも選択エピタキシャ
ル層を形成することにより更に選択性、平坦性が向上す
るものである。In other words, in silicon selective epitaxial growth using a silicon oxide film as a mask material, selectivity and flatness are affected by the area ratio of silicon to silicon oxide (8i/S1o,), and the area of Si//5io2 Since the selectivity and flatness are improved by increasing the ratio, the selectivity and flatness are further improved by forming a selective epitaxial layer in areas other than the original semiconductor device.
以上説明したように、この発明によれば、絶縁膜を選択
的に除去して形成した開口部に減圧下でのエピタキシャ
ル成長技術により半導体層を形成して半導体素子を設け
るという簡単な工程により、選択酸化法による素子間分
離技術では不可避のバーズビーク、バーズビークをなく
し、また活性領域を構成する半導体層についても周辺部
の盛り土がりを抑制することができ、従来法による場合
に比較してより高密度の集積化が可能で多層配線の応用
も容易な半導体装置を製造することが可能となる。As explained above, according to the present invention, a semiconductor layer is formed in an opening formed by selectively removing an insulating film by an epitaxial growth technique under reduced pressure, and a semiconductor element is provided through a simple process. The device isolation technology using the oxidation method eliminates the unavoidable bird's beak and bird's beak, and also suppresses the mounding around the semiconductor layer that makes up the active region, allowing for higher density isolation compared to the conventional method. It becomes possible to manufacture a semiconductor device that can be integrated and can easily be applied to multilayer wiring.
第1図は選択エピタキシャル層の平坦性の圧力依存性の
一例を示すグラフ、第2図はその場合の平坦性を説明す
るだめの図、第3図および第4図はこの発明の一実施例
を適用した半導体装置の各工程断面図である。
(11)・・・・P形半導体基板、(12)・・・・酸
化膜、(13)・・・・エピタキシャル層、(14)、
(15)・・・・ソース、ドレイン、(16)・・・・
ケート。
代理人 葛野信−
滉式縛
手続補正書(自発)
2、発明の名称
半導体装置の製造方法
3、補正をする者
事件との関係 特許出願人
代表者片山仁へ部
4、代理人
54 補正の対象
明細書の発明の詳細な説明の欄
6 補正の内容
(1)明細書第3頁第16〜17行、第20行の「キャ
リーガス」を「キャリヤーガス」と補正する。
(2)同書第4頁第15行の「キャリーガス」を「キャ
リヤーガス」と補正する。
(3)同書第5頁第5行の[キャリーガス]を「キャリ
ヤーガス」と補正する。
(4)同書同頁第16〜17行の「チャネルドープ」を
「チャネルカット」と補正する。
以 上FIG. 1 is a graph showing an example of pressure dependence of the flatness of a selective epitaxial layer, FIG. 2 is a diagram for explaining the flatness in that case, and FIGS. 3 and 4 are examples of the present invention. FIG. 3 is a cross-sectional view of each step of a semiconductor device to which the method is applied. (11)...P-type semiconductor substrate, (12)...oxide film, (13)...epitaxial layer, (14),
(15)...source, drain, (16)...
Kate. Agent Makoto Kuzuno - Written amendment to formal binding procedure (voluntary) 2. Name of the invention Method for manufacturing a semiconductor device 3. Relationship with the person making the amendment Hitoshi Katayama, representative of the patent applicant Department 4, Agent 54 Amendment Column 6 for Detailed Description of the Invention in the Target Specification Contents of Amendment (1) "Carry gas" in lines 16-17 and line 20 on page 3 of the specification is corrected to "carrier gas." (2) "Carry gas" on page 4, line 15 of the same book is corrected to "carrier gas." (3) [Carry gas] on page 5, line 5 of the same book is corrected to "carrier gas." (4) "Channel dope" in lines 16-17 of the same page of the same book is corrected to "channel cut."that's all
Claims (3)
して配列してなる半導体装置の製造方法において、基板
上に絶縁膜を形成する工程と、この絶縁膜の半導体素子
形成部分を選択的に除去して基板を露出させる工程と、
露出した基板上に減圧下でのエピタキシャル成長技術に
よって半導体層を形成する工程とを含み、上記半導体層
に半導体素子を形成することを特徴とする半導体装置の
製造方法。(1) In a method of manufacturing a semiconductor device in which semiconductor elements are arranged and separated from each other by an inter-element isolation insulating film, a process of forming an insulating film on a substrate and selectively forming a semiconductor element forming portion of this insulating film is performed. removing to expose the substrate;
1. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor layer on an exposed substrate by epitaxial growth technology under reduced pressure, and forming a semiconductor element on the semiconductor layer.
とする特許請求の範囲第1項記載の半導体装置の製造方
法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the pressure is 80 torr or less.
を特徴とする第1項又は第2項記載の半導体装置の製造
方法。(3) The method for manufacturing a semiconductor device according to item 1 or 2, characterized in that the semiconductor element is an MO8 type semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14440482A JPS5933847A (en) | 1982-08-18 | 1982-08-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14440482A JPS5933847A (en) | 1982-08-18 | 1982-08-18 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5933847A true JPS5933847A (en) | 1984-02-23 |
Family
ID=15361379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14440482A Pending JPS5933847A (en) | 1982-08-18 | 1982-08-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5933847A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0222225A2 (en) * | 1985-10-31 | 1987-05-20 | International Business Machines Corporation | Dielectrically isolated integrated circuit device and method of making |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591815A (en) * | 1978-12-29 | 1980-07-11 | Fujitsu Ltd | Silicon epitaxial growth |
JPS568814A (en) * | 1979-07-02 | 1981-01-29 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Epitaxial growth of silicon under reduced pressure |
-
1982
- 1982-08-18 JP JP14440482A patent/JPS5933847A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591815A (en) * | 1978-12-29 | 1980-07-11 | Fujitsu Ltd | Silicon epitaxial growth |
JPS568814A (en) * | 1979-07-02 | 1981-01-29 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Epitaxial growth of silicon under reduced pressure |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0222225A2 (en) * | 1985-10-31 | 1987-05-20 | International Business Machines Corporation | Dielectrically isolated integrated circuit device and method of making |
US4908691A (en) * | 1985-10-31 | 1990-03-13 | International Business Machines Corporation | Selective epitaxial growth structure and isolation |
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