JPS5923612A - Manufacture of piezoelectric resonator - Google Patents
Manufacture of piezoelectric resonatorInfo
- Publication number
- JPS5923612A JPS5923612A JP13334982A JP13334982A JPS5923612A JP S5923612 A JPS5923612 A JP S5923612A JP 13334982 A JP13334982 A JP 13334982A JP 13334982 A JP13334982 A JP 13334982A JP S5923612 A JPS5923612 A JP S5923612A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- substrate
- film
- piezoelectric
- piezoelectric thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010409 thin film Substances 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 20
- 239000003795 chemical substances by application Substances 0.000 claims 1
- FHTQCUNSKSWOHF-UHFFFAOYSA-N ethyl carbamate;silicon Chemical compound [Si].CCOC(N)=O FHTQCUNSKSWOHF-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 2
- 238000004544 sputter deposition Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はシリコンウェハーなどの基板士に圧電性薄膜を
形成するとともに圧電性薄膜と対向するシリコンウェハ
ーの他面に異方性エツチング処理で凹部を形成した、バ
ルク波を利用した高周波用圧電共振子の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for producing bulk waves by forming a piezoelectric thin film on a substrate such as a silicon wafer, and forming recesses by anisotropic etching on the other side of the silicon wafer facing the piezoelectric thin film. The present invention relates to a method of manufacturing the high-frequency piezoelectric resonator used.
このような圧電共振子は、ｊ’ｙｕＮ、ｕＡＭ４ｒＮＴ
ｈＬＭＯＤＥ ＶＨＦ／ＵＨＦ ＢＵＬＫ ＡＯＯＵＳ
ＴＩＣｗｈｖｒ。Such piezoelectric resonators are j'yuN, uAM4rNT
hLMODE VHF/UHF BULK AOOUS
TICwhvr.
ＲＦｉＳＯＮＡＴＯＲ８ＡＮＤ Ｆ工ＬＴ用、ＦＥＩ
ＯＮ ８工ＬＩ−０ＯＮＪ Ｈ’８０ ＵＬＴ
ＲＡ８ＯＮｌＣ日ＹＭＰＯ８ＩＵＭＰ、８２９〜８５３
や「ｚｎｏ／ＳｉＯｔ−ＤＩＡＰ）ＩＲＡＧＭｏｏＭＰ
ＯＥＩＩＴｌｎ １１８ＯＮＡＴＯＦ ＯＮ Ａ
８工り工０ＯＮＷＡＦＢＩＩＪ ＥＬＩ！ｔＯＴ
ＦＯＮ工Ｏ８ＬＦｉＴＴ］Ｉｎｓ ９ｔｈＪｕｌｙ
１９８１ ｖｏｌ、１７ Ｎｏ、１４ Ｆ、５０７〜
５０９に開示されており、第１図および第２図に示す構
造をとる。RFiSONATOR8AND F engineering LT, FEI
ON 8 Engineering LI-0ONJ H'80 ULT
RA8ONlCdayYMPO8IUMP, 829-853
and “zno/SiOt-DIAP) IRAGMooMP
OEIITln 118ONATOF ON A
8 machinist 0ONWAFBIIJ ELI! tOT
FON Engineering O8LFiTT] Ins 9thJuly
1981 vol, 17 No, 14 F, 507~
509, and has the structure shown in FIGS. 1 and 2.
第１図の共振子は、シリコンウエノ・−１の一方面１ａ
上から所定の深さだけボロン等をドープしたく記号２で
示す）のち、他方面１ｂを異方性エツチング処理にて凹
部３を形成し゛〔シリコンウェハー１に厚みの薄い部分
（ダイアフラムハＣを構成し、次１へてシリコンウェハ
ー１の一方面１ａ上にダイアフラム１Ｃ上を含んでＡｔ
’などを蒸着し゛〔下部電極４を形成し、この１＃Ｌ極
４を含むシリコンウェハー１上にスパッタリングなどに
よりＺｎＯなどの圧電性薄膜５を形成し、さらに圧電性
薄膜５上に少なくとも下部゛電極４と対向させｒＡ１な
どを蒸着し゛Ｃ上部電極６を形成したもので、電極４゜
６間にｒｌｌ倍信号加え゛Ｃ圧電性薄膜５の１に１軍効
果によりその薄膜５を振動させることにより、圧電性薄
膜５とシリコンウェハー１のダイアフラム１Ｃとの複合
体を振動させ、その複合体の厚みＪ辰動を利用し゛Ｃ１
０Ｃ１０Ｏ以上の高周波数領域で有利ＫＴｉｂ作させ得
るものである。The resonator in Fig. 1 is one side 1a of silicon Ueno-1.
After doping boron or the like to a predetermined depth from above (indicated by symbol 2), the other surface 1b is anisotropically etched to form a recess 3. At step 1, At
A piezoelectric thin film 5 such as ZnO is formed on the silicon wafer 1 including this 1#L pole 4 by sputtering, and then at least a lower electrode 4 is formed on the piezoelectric thin film 5. An upper electrode 6 is formed by vapor depositing rA1 or the like facing the electrode 4, and an rll multiplied signal is applied between the electrodes 4 and 6 to cause the thin film 5 to vibrate due to the 1st force effect on the 1st layer of the piezoelectric thin film 5. , the composite of the piezoelectric thin film 5 and the diaphragm 1C of the silicon wafer 1 is vibrated, and the thickness J of the composite is used to vibrate C1.
KTib can be produced advantageously in a high frequency region of 0C10O or higher.
上述した圧電共据子は、シリコンウエノ・−１に異方性
エツチング処理を施し”［Ｅｌｌのダイアフラム１Ｃを
作成したのち、下部’ｆＫ、極ａ、圧電性薄膜５および
上部電極６を形成するようにしＣＩＱる。The above-mentioned piezoelectric co-installation is made by applying anisotropic etching to silicon Ueno-1 to create the diaphragm 1C, and then forming the lower fK, the pole a, the piezoelectric thin film 5, and the upper electrode 6. I want to do CIQ.
しかし、そのダイアフラム１Ｃけ厚みが数μｍで機械的
強度が弱いものであるから、ダイアフラム１Ｃ作成後の
超音波洗浄の工程、上、下部ｔｔ！、）Ｍや圧′ｔは性
薄膜形成の工程におＬＱ−（，１１１：産的に処理する
とダイアフラム１Ｃが破損する率が高−〇と（＾う事実
が見１＾出された。しかも、後工程だけでなく、異方性
エツチング処理を施す際にもダイアフラム１Ｃが破損し
、シリコンウェハー１が使用不能になる率も高く、全体
とし°Ｃの破損する率は非常に高いものである。゛また
、上記した構造では、工程を逆転させ′〔、圧電性薄膜
５を形成したのちダイアフラム１Ｃを作成しようとした
場合、異方性エツチング処理時に圧電性薄膜５や電極４
，６が、ビロカテロール、エチレンジアミンおよヒ水か
らなるｔ方性エツチング液におかされ圧電機能を果たさ
なくなる。However, the thickness of the diaphragm 1C is several μm and its mechanical strength is weak, so the ultrasonic cleaning process after making the diaphragm 1C, the upper and lower parts! , ) M and pressure 't are important in the process of forming a thin film. , the diaphragm 1C is damaged not only in the post-process, but also during the anisotropic etching process, and there is a high rate of silicon wafer 1 becoming unusable, and the overall rate of damage in °C is extremely high. In addition, in the above structure, if the process is reversed and the piezoelectric thin film 5 is formed and then the diaphragm 1C is created, the piezoelectric thin film 5 and the electrode 4 are removed during the anisotropic etching process.
, 6 loses its piezoelectric function when exposed to a t-tropic etching solution consisting of virocaterol, ethylenediamine, and arsenic water.
第２図のものは、シリコンウエノＳ−７の一方面上に８
１０．の膜８を形成し、他方面に異方性エツチング処理
を施し゛（ＥｌｉＯ，膜８まで達する凹部９を形成する
ことにより８１０．ダイアフラム８ａを作成したのち、
第１図のものと同様に下部電極４１圧電性薄膜５および
上部ｔ、ＩＭ６を順次形成するようにしたものである。The one in Figure 2 is 8 on one side of Silicon Ueno S-7.
10. A film 8 is formed, and the other surface is subjected to an anisotropic etching process (EliO), by forming a recess 9 that reaches the film 8 (810). After creating a diaphragm 8a,
Similar to the one shown in FIG. 1, the lower electrode 41, the piezoelectric thin film 5, the upper part t, and the IM 6 are sequentially formed.
この圧電共振子の製造方法も８１０．のダイアフラム８
ａが破損しやす１Ｑという欠点がある。The manufacturing method of this piezoelectric resonator is also 810. diaphragm 8
There is a drawback that 1Q is easily damaged.
第３図は、既に本件出願人が提案したもので、一方面上
から所定深さだけボロン等をドープした（記号１１で示
す）シリコンウニ、−−１０の一方向ＶＣ８ｉＯ，膜１
２を形成し、他方面を異方性エツチング処理し・〔ドー
プ層まで凹部１３を形成することにより、Ｓｉとｓｉｏ
、の二層構造からなるダイアフラム１４を作成したのち
、第１図のものと同様に下部電極４、圧’ｔ（１，性薄
膜５および上部７１ｔ（執が破損しやす一＾という欠点
がある。FIG. 3 shows a silicon sea urchin doped with boron or the like to a predetermined depth from one side (indicated by symbol 11), a unidirectional VC8iO film of --10, which has already been proposed by the applicant.
2 is formed, and the other side is anisotropically etched. [By forming a recess 13 up to the doped layer, Si and
After creating a diaphragm 14 consisting of a two-layer structure, similar to the one in FIG. .
本発明は、上述した従来技術の欠点を除去したもので、
ダイアフラムの破損を少なくして、収率を向上させ得る
製造方法を提供することを目的とする。The present invention eliminates the above-mentioned drawbacks of the prior art, and
It is an object of the present invention to provide a manufacturing method that can reduce damage to a diaphragm and improve yield.
以下、本発明の実施例を図面を参照しつつ詳述する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第４図を参照しＣ１まず、一方面２ＯＮから所定深さま
でボロンなどをドープした（ドープ層を２１で示す）シ
リコンウエノ５−２０を用意する。Referring to FIG. 4, C1: First, a silicon wafer 5-20 doped with boron or the like (the doped layer is indicated by 21) from one side 2ON to a predetermined depth is prepared.
（同図（ａ））このシリコンウエノ・−２０の一方向２
０ａ上に、８１とは逆付号の温度特性をもつ８１０１ｇ
２２ ヲスパッタリング、イオンブレーティング、ＯＶ
Ｄなどで形成する。（同図（ｂ））次（八で、８１０、
膜２２上に、ｈｅ、Ｏｕ、Ａｇ５Ａｕなどの金属を蒸着
して下部電極２６を形成し、この下部電極２３を含む５
１０２膜２２上に、スパッタリング、イオンプレーディ
ング、ＣｖＤなどの方法によシ圧電性のＺｎＯ膜２膜外
４成し、さらに、下部電極２６と一部を対向させ°（Ｚ
ｎＯ膜２膜上４上Ｓ１０！膜２２上にかけ’ＣＡ １７
、Ｏｕ、Ａｇ、Ａｕなどからなる上部電極２５を蒸着等
によシ形成する。（同図（→）次に次工程で利用する異
方性エツチング液におかされない、ＡＩ、Ｏｊ、Ｓｉ、
Ｎ４．Ｓｉｎ、などからなるｕｍ体膜２６を、ＺｎＯ膜
２膜外４、下部電極２３．２５の全体の覆うよう罠、ス
パッタリング、イオンブレーティング、ＯＶＤ等により
形成する。（同図（４））この誘電体膜２６の形成後に
、シリコンウェハー２０の他方面２０ｂを、例えばピロ
カテロール、エチレンジアミン、水からなるエツチング
液によυ異方性エツチング処理し′〔、ドープ層２１ま
で凹部２７を形成する。（同図（ｅ））次に、 銹４体
膜２６の一部をエツチングし′〔上、下部電極２５．２
５を露出させ、コンタクトホール２８．２９を形成する
。（同図（ｅ））なお、ドープ層２１ 、Ｓｉｎ、膜２
２ＺｎＯ膜２４は（八ずれも厚みが数１１ｍと非常に薄
く、また凹部はＩｒｎｍ角以下の非常に小さいものであ
り、一方、シリコンウェハー２０は通常直径数インチの
ものヲ用１．、シリコンウェハー２０上に多数の共振子
を一括し゛〔作成し、個々の共振子に切出し・〔１＾く
ものである。(Figure (a)) One direction 2 of this silicon ueno-20
8101g, which has temperature characteristics opposite to 81 on 0a.
22 Sputtering, ion blating, OV
Form with D etc. (Figure (b)) Next (8, 810,
A lower electrode 26 is formed on the film 22 by depositing metal such as he, Ou, Ag5Au, etc.
A piezoelectric ZnO film 2 is formed on the 102 film 22 by a method such as sputtering, ion plating, or CVD, and a part of the ZnO film 2 is made to face the lower electrode 26 (Z
S10 on nO film 2 film 4 film! 'CA 17 applied over the membrane 22
An upper electrode 25 made of , Ou, Ag, Au, etc. is formed by vapor deposition or the like. (Same figure (→) Next, AI, Oj, Si,
N4. An umum body film 26 made of Sin, etc. is formed by trapping, sputtering, ion blasting, OVD, etc. so as to cover the entire ZnO film 2, outer film 4, and lower electrode 23.25. ((4) in the same figure) After forming the dielectric film 26, the other surface 20b of the silicon wafer 20 is subjected to an anisotropic etching process using an etching solution consisting of, for example, pyrocaterol, ethylenediamine, and water. A recess 27 is formed up to the point. ((e) in the same figure) Next, a part of the four-layer film 26 is etched' [upper and lower electrodes 25.2
5 is exposed and contact holes 28 and 29 are formed. ((e) in the same figure) Note that the doped layer 21, Sin, film 2
The 2ZnO film 24 is very thin, with a thickness of several 11 m, and the recess is very small, less than the Irnm angle.On the other hand, the silicon wafer 20 is usually a silicon wafer with a diameter of several inches. A large number of resonators are created all at once on the 20, and then cut out into individual resonators.
本実施例によれば、シリコンウェハー２０、Ｓ１０を膜
２２、ｚｎＯ膜２４、上、下部電極２３．２５からなる
多層構造の状態で異方性エツチング処理を施すようにし
、しかもドープ層２１に５１０２膜２２が接着され、こ
の５ｉｎｊ膜２２にＺｎＯ膜２膜外４が接着され、かつ
その接着がスパッタリングなどで強固になされＣ（へる
ので、異方性エツチング処理時にドープ層２１や５１０
２膜２２のダイアフラムの部分が破損する率が非常に少
なくなる。また、ダイアフラムがドープ層２１、Ｓｉ０
，１摸２２、ＺｎＯ膜２膜外４層構造でｆｉｌ成され、
かつ異方性エツチング処理しｆｃ後の工程数が少なくな
るので、後工程における破損の確率が大ｒｌＪに小さく
なる。According to this embodiment, the anisotropic etching process is performed on the silicon wafer 20, S10 in the state of a multilayer structure consisting of the film 22, the ZnO film 24, and the upper and lower electrodes 23, 25. The film 22 is adhered, and the ZnO film 2 and the outer film 4 are adhered to this 5 inch film 22, and the adhesion is made strong by sputtering or the like.
The probability that the diaphragm portion of the two membranes 22 is damaged is greatly reduced. Further, the diaphragm is a doped layer 21, Si0
, 1, 22, a filtration structure consisting of 2 ZnO films, 2 outer layers, and 4 layers,
In addition, since the number of steps after anisotropic etching and fc is reduced, the probability of damage in subsequent steps is greatly reduced.
上記実施例におい゛〔、下部１１イ極２３および上部電
極２５を、異方性エツチング液におかされな−へＡｕｌ
Ａｇ、Ｏｕ、Ｔａ、Ｏｒなどの金属材料で形成し、誘電
体膜２６の形成時に両電極２３．２５の一部を露出させ
Ｃおくと、コンタクトホールが不要となる。In the above embodiment, the lower electrode 23 and the upper electrode 25 are exposed to the anisotropic etching solution.
If the electrodes 23 and 25 are made of a metal material such as Ag, Ou, Ta, Or, etc., and a portion of both electrodes 23 and 25 are exposed when forming the dielectric film 26, a contact hole is not required.
第５図は他の実施例を示し、上記実施例との相違点は、
第１図のものに相当する構造であつ゛Ｃ１異方性エツチ
ング処理の後から誘電体膜２６をエツチングし“〔除去
するようにしたものである。すなわち、ドープ層２１を
形成したどりコンウエノ・−２０を用意しく第５図（ａ
）） 、ウエノ・−２０上に下部１１ｔ４Ｍ２３．、Ｚ
ｎ０ＩＩａｆ２４、上部電極２５を形成した（同図（ｂ
））のち、誘電体膜２６を形成しく同図（ｃ））、その
後に、異方性エツチング処理を施し°Ｃ四部２７を形成
しく同図（→）、次−＾で選択エツチングを施し゛Ｃ誘
電体膜２６のみを除去する。（同図（θ））本実施例も
上記実施例と同様の効果が得られる。FIG. 5 shows another embodiment, and the differences from the above embodiment are as follows.
This structure corresponds to the one shown in FIG. 1, in which the dielectric film 26 is etched and removed after the C1 anisotropic etching process. That is, the doped layer 21 is formed and then removed. Figure 5 (a)
)), lower part 11t4M23. on Ueno-20. ,Z
n0IIaf24, and an upper electrode 25 was formed (see figure (b)
)) After that, a dielectric film 26 is formed (FIG. 2(c)), and then an anisotropic etching process is performed to form a fourth part 27. Only the C dielectric film 26 is removed. ((θ) in the same figure) This example also provides the same effects as the above example.
上記各実施例では圧電性ｒＷ膜とし°〔ＺｎＯ膜を例示
しＣいるが、本発明によればＡｅＮ、ｃａｓなど他の圧
電性薄膜を用（八°〔もよい。また本発明における基板
は、ドープ層を作成したシリコンウェハー、８１０．膜
を形成したシリコンウェハー、あるＩ＾はドープ層を作
成しかつＳ１０！膜を形成したシリコンウェハーでもよ
く、要は少なくともシリコンウェハーを含む基板であれ
ばよい。さらに本発明では、特にシリコンウェハーにド
ープ層を作成 ′した場合には、そのドープ層を
下部電極とし°Ｃ動作させ、ＡＮ蒸着などによる１部電
極を省略することができる。In each of the above embodiments, the piezoelectric rW film is used as an example. However, according to the present invention, other piezoelectric thin films such as AeN and CAS may be used. , a silicon wafer on which a doped layer is formed, a silicon wafer on which a 810. film is formed, and a certain I^ may be a silicon wafer on which a doped layer is formed and a S10! film is formed, in short, as long as the substrate includes at least a silicon wafer. Further, in the present invention, especially when a doped layer is formed on a silicon wafer, the doped layer can be used as a lower electrode and operated at °C, and some electrodes by AN evaporation or the like can be omitted.
本発明は、以上説明したように、異方性エツチング処理
前のシリコンウエノ・−をバむ基板上に圧電性薄膜など
を形成し、その圧電性薄膜を（夏うよに誘電体薄膜を形
成し、その陵から異方性エツチング処理し“〔ダイアフ
ラムを作成するようにし′Ｃいるので、ダイアフラムの
破損が著しく減少し、収率が向上する。As explained above, in the present invention, a piezoelectric thin film or the like is formed on a substrate that is coated with silicone material before being anisotropically etched, and then the piezoelectric thin film is replaced with a dielectric film. Since the ridges are anisotropically etched to form a diaphragm, damage to the diaphragm is significantly reduced and the yield is improved.
第１図、第２図および第３図は従来の圧電共振子の断面
図、第４図は本発明に基づく製造方法の各工程の説明図
、第５図は他の製造方法の各工程の説明図である。
２０はシリコンウェハー、２４は圧電性薄膜、２３．２
５は電極、２６は誘電体薄膜、２７は凹部である。
特許出願人
株式会社 村山製作所
第２図
躬３胆
第 ５ 図1, 2, and 3 are cross-sectional views of a conventional piezoelectric resonator, FIG. 4 is an explanatory diagram of each step of the manufacturing method based on the present invention, and FIG. 5 is an explanatory diagram of each step of another manufacturing method. It is an explanatory diagram. 20 is a silicon wafer, 24 is a piezoelectric thin film, 23.2
5 is an electrode, 26 is a dielectric thin film, and 27 is a recess. Patent applicant Murayama Seisakusho Co., Ltd. Figure 2, Figure 3, Figure 5
Claims (1)
方面上に、下部電極、圧電性薄膜および上部電極を順次
形成したのち、少なくとも圧電性薄膜を覆うように、異
方性エツチング液におかされな１へ誘電体薄膜を形成し
、次いで基板の他方面に異方性エツチング処理を施し′
Ｃ凹部を形成するようＫしたことを特徴とする圧電共振
子の製造方法。 （２）少なくともシリコンウェハーを含む基板の一方面
上に、下部電極、圧α性薄膜および上部電極を順次形成
したのち、これら下部電極、圧電性薄膜および上部７ト
極の全体を覆うように１異方性エツチンダ液におかされ
ない誘電体薄膜を形成し、次−へで、基板の他方面に異
方性エツチング処理を施し゛Ｃ四部を形成するとともに
、誘電体薄膜の一部にエツチング処理を処しＣ上、下部
電極の一部を露出させるようにしたことを特徴とする圧
電共振子の製造方法。 （８） 少なくともシリコンウエノ・−を含む基板の
一方面上に、下部ｉｔｔ極、圧電性薄膜および下部電極
を順次形成したのち、少なくとも圧電性薄膜を覆うよう
に、異方性エツチング液におかされな１へ誘電体薄膜を
形成し、次いで基板の他方面にゲ４方性エツチング処理
を施し”で四部を形成したのち、誘電体薄膜をエツチン
グ処理に・Ｃ除去するようにしたことを特徴とする圧電
共振子の製造方法。 （４）前記圧電性薄膜はＺｎＯ膜である特許請求の範囲
第（１）項、第（２）項または第（８）項記載の圧電共
振子の製造方法。[Scope of Claims] (1) After a lower electrode, a piezoelectric thin film, and an upper electrode are sequentially formed on one side of a substrate including at least -ff a silicon wafer, a A dielectric thin film is formed on the first surface of the substrate in an anisotropic etching solution, and then an anisotropic etching process is applied to the other surface of the substrate.
1. A method for manufacturing a piezoelectric resonator, characterized in that K is formed to form a C recess. (2) After sequentially forming a lower electrode, a piezoelectric thin film, and an upper electrode on one side of a substrate including at least a silicon wafer, a layer is formed so as to cover the entire lower electrode, piezoelectric thin film, and upper seven electrodes. A dielectric thin film that is not affected by the anisotropic etching agent is formed, and in the next step, an anisotropic etching process is performed on the other side of the substrate to form the fourth part of the substrate, and a part of the dielectric thin film is also etched. A method for manufacturing a piezoelectric resonator, characterized in that a part of the upper and lower electrodes is exposed in the process C. (8) After sequentially forming a lower itt electrode, a piezoelectric thin film, and a lower electrode on one side of a substrate containing at least silicon urethane, the electrodes are soaked in an anisotropic etching solution so as to cover at least the piezoelectric thin film. A dielectric thin film is formed on one surface of the substrate, and then a four-part etching process is performed on the other side of the substrate to form four parts, and then the dielectric thin film is removed by etching process. (4) The method for manufacturing a piezoelectric resonator as set forth in claim (1), (2), or (8), wherein the piezoelectric thin film is a ZnO film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13334982A JPS5923612A (en) | 1982-07-29 | 1982-07-29 | Manufacture of piezoelectric resonator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13334982A JPS5923612A (en) | 1982-07-29 | 1982-07-29 | Manufacture of piezoelectric resonator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5923612A true JPS5923612A (en) | 1984-02-07 |
Family
ID=15102639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13334982A Pending JPS5923612A (en) | 1982-07-29 | 1982-07-29 | Manufacture of piezoelectric resonator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923612A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6174954U (en) * | 1984-10-19 | 1986-05-21 | ||
| JPH04241505A (en) * | 1991-01-14 | 1992-08-28 | Murata Mfg Co Ltd | Piezoelectric thin film vibrator |
| US6345424B1 (en) * | 1992-04-23 | 2002-02-12 | Seiko Epson Corporation | Production method for forming liquid spray head |
| US7594308B2 (en) * | 2004-10-28 | 2009-09-29 | Brother Kogyo Kabushiki Kaisha | Method for producing a piezoelectric actuator and a liquid transporting apparatus |
| US20100237750A1 (en) * | 2009-03-19 | 2010-09-23 | Fujitsu Limited | Piezoelectric thin film resonator, filter, communication module and communication device |
| US20110115338A1 (en) * | 2001-02-12 | 2011-05-19 | Agere Systems Inc. | Methods of Fabricating a Membrane With Improved Mechanical Integrity |
| JP2012060259A (en) * | 2010-09-06 | 2012-03-22 | Fujitsu Ltd | Manufacturing method of vibrator, vibrator and oscillator |
| US8230562B2 (en) * | 2005-04-06 | 2012-07-31 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Method of fabricating an acoustic resonator comprising a filled recessed region |
| US9859205B2 (en) | 2011-01-31 | 2018-01-02 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor device having an airbridge and method of fabricating the same |
-
1982
- 1982-07-29 JP JP13334982A patent/JPS5923612A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6174954U (en) * | 1984-10-19 | 1986-05-21 | ||
| JPH04241505A (en) * | 1991-01-14 | 1992-08-28 | Murata Mfg Co Ltd | Piezoelectric thin film vibrator |
| US6345424B1 (en) * | 1992-04-23 | 2002-02-12 | Seiko Epson Corporation | Production method for forming liquid spray head |
| US20110115338A1 (en) * | 2001-02-12 | 2011-05-19 | Agere Systems Inc. | Methods of Fabricating a Membrane With Improved Mechanical Integrity |
| US8225472B2 (en) * | 2001-02-12 | 2012-07-24 | Agere Systems Inc. | Methods of fabricating a membrane with improved mechanical integrity |
| US7594308B2 (en) * | 2004-10-28 | 2009-09-29 | Brother Kogyo Kabushiki Kaisha | Method for producing a piezoelectric actuator and a liquid transporting apparatus |
| US8230562B2 (en) * | 2005-04-06 | 2012-07-31 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Method of fabricating an acoustic resonator comprising a filled recessed region |
| US20100237750A1 (en) * | 2009-03-19 | 2010-09-23 | Fujitsu Limited | Piezoelectric thin film resonator, filter, communication module and communication device |
| US8240015B2 (en) * | 2009-03-19 | 2012-08-14 | Taiyo Yuden Co., Ltd. | Method of manufacturing thin film resonator |
| US9240769B2 (en) | 2009-03-19 | 2016-01-19 | Taiyo Yuden Co., Ltd. | Piezoelectric thin film resonator, filter, communication module and communication device |
| JP2012060259A (en) * | 2010-09-06 | 2012-03-22 | Fujitsu Ltd | Manufacturing method of vibrator, vibrator and oscillator |
| US9859205B2 (en) | 2011-01-31 | 2018-01-02 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor device having an airbridge and method of fabricating the same |
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