JPS59191927A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent a ringing phenomenon and to accelerate the synchronization by changing the input signal to be applied to a flip-flop of a synchronizing circuit with the given clock signal. CONSTITUTION:An AND circuit 4 uses an inverted signal Q, a non-synchronizing signal I and a clock signal CL of an FF7 as inputs and therefore delivers an output to an OR circuit 6 when the FF7 is reset together with signals CL and I set at 1, respectively. Then the circuit 4 produces a clock signal CLK and inverts the FF7 to set it. An AND circuit 5 is actuated when the FF7 is set and delivers an output to the circuit 6 when signals I and CL are set at 0 and 1, respectively. Then the circuit 5 delivers the signal CLK to the FF7 to invert and reset the FF7. Therefore the cycle of the clock CL can be set at the time obtained by adding the effective time of the pulse width to the element delay, thereby accelerating the synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a synchronization circuit that synchronizes an asynchronous signal to a signal of a predetermined period.

(b) Prior art and problems Asynchronous (period undefined) signal S emitted from the first device
, is often converted (synchronized) into a synchronization signal S2 of a predetermined period and used to control the second device. As one method for such synchronization, a flip-flop is provided on the second device side, an asynchronous signal S from the first device is inputted to the input terminal of the flip-flop, and a clock signal CL of a predetermined period is used to synchronize the flip-flop with a clock signal CL of a predetermined period. There is a method of using the output of the flip-flop as a control signal by setting a flip-flop.

In this conventional method, if the flip-flop is set by the clock signal CL when the set-up time of the input asynchronous signal S1 is not correctly guaranteed, a ringing phenomenon may occur and the output signal waveform may be disturbed. many. In order to prevent this, the conventional method connects flip-flops in two stages, which makes the circuit configuration complicated, and has the disadvantage that it takes twice the maximum clock signal period to obtain the synchronization signal.

(c) Purpose of the invention The present invention has been made to solve the above-mentioned drawbacks.
The purpose of this invention is to provide a synchronization circuit that facilitates synchronization.

(d) Structure of the Invention The present invention provides a circuit that synchronizes an asynchronous binary signal input at an irregular period with a synchronous signal of a predetermined period and outputs the synchronized signal, which comprises a flip-flop driven by a clock signal of the predetermined period; a first output signal from one output end of the flip-flop, the clock signal, and the asynchronous binary signal; an AND circuit, a second output signal from the other output terminal of the flip-flop, the clock signal, and the asynchronous binary signal are input, and when the asynchronous binary signal is at a second signal level, the clock signal is input. a second AND circuit, one input terminal of which is connected to the output terminal of the second N0 circuit, the other input terminal of which is connected to the output terminal of the first AND circuit, and the output terminal of which is connected to the flip-flop; This is a synchronous circuit characterized by comprising an OR circuit connected to a clock input terminal of the synchronous circuit.

(e) Examples of the invention The present invention will be explained below with reference to the drawings. 1 is a block diagram explaining an embodiment of the present invention, and FIG. 2 is a signal waveform diagram), 1 and 2 are a control device, 3 is an inverter, 4 and 5 are an AND circuit, 6 is an OR circuit, 7 is flip frog,
A, B, a, b are signal levels.

CL, CLK, CLK+, CLK2 are clock signals, ■ is an asynchronous signal, R8 is a reset signal, S is a synchronous signal, T is pulse width + j++ j2+ t3+ t4 is time, which is processed by clock signal CL. This is an embodiment in which the self-control operation is performed by the synchronization signal S obtained by synchronization. In such a case, conventionally, two flip-frogs connected in cascade (two-stage connection) are provided on the control device 2 side to prevent the ringing phenomenon. The present invention aims to realize a synchronous circuit equivalent to the conventional method by using only one flip-flop. In the embodiment, an example of a JK-type IJ knob flop will be explained.

In FIG. 1, the AND circuit 4 inputs the output signal Q1 of the knob flop (hereinafter referred to as FF) 7 and the clock signal CL, so when FF7 is in the reset state, the asynchronous signal I is at the signal level At the time of B, the clock signal CL passes through the OR circuit 6, becomes the clock signal CLK, and sets the FF7. FIG. 2 shows the time relationship and signal waveform. As shown in FIG. 2(b), at time t.

When the signal level of the asynchronous signal I becomes B and the clock signal CL falls at time t2 as shown in FIG. 2(a), the AND circuit 4 receives the clock signal as shown in FIG. 2(c). The signal CLK is generated. This clock signal CLK
Since FF7 in FIG. 1 is set by FF1, the synchronizing signal S is inverted from signal level a to b on the output side, as shown in FIG. 2(d).

In the embodiment, the pulse width of the synchronization signal CLKI is as shown in FIG.
As shown in c), it is 9 ns, and it operates normally when the pulse width is greater than this value.

On the other hand, the AND circuit 5 in FIG. 1 is a gate for resetting the FF 7, and its circuit operation is as follows. Second
As shown in the figure, time 1. When the asynchronous signal I is inverted to the signal level A, the falling edge of the clock signal CL generates a cyclic signal CLK2, which resets υFF7. The output of the synchronous signal is shown in Figure 2(d).
The signal level is inverted from b to a as shown in FIG.

(f) Effects of the invention As described above, the present invention provides synchronization (outputting a synchronization signal).
Since the input signal to the flip-flop that forms the circuit changes depending on the applied clock signal, ringing phenomenon can be prevented, and the period of the clock signal is equal to the delay time (approximately 7 ns) of the element (for example, SN748112). Since the time required is the sum of the effective time of the pulse width,
It has the advantage of being able to perform synchronization quickly.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining one embodiment of the present invention, and FIG.
The figure is a signal waveform diagram for explaining one embodiment of the present invention, and the gradient signs used in the figure are as follows. 1.2 is a control device, 3 is an inverter, 4.5 is an AND circuit, 6 is an OR circuit, 7 is a flip-flop, A. B, a, b are signal levels, CL, CLK, CLK,
, CLK2 is a clock signal, ■ is an asynchronous signal, R8 is a reset signal, S is a synchronous signal, T is a pulse width, tl. t2. t8. t4 indicates time.

Claims (1)

[Claims] In a circuit that synchronizes an asynchronous binary signal input at an irregular period with a synchronous signal of a predetermined period and outputs the synchronized signal, a flip-flop driven by the clock signal of the predetermined period;
A first input circuit that receives a fourth output signal from one output end of the flip-flop, the clock signal, and the asynchronous binary signal, and allows the clock signal to pass when the asynchronous binary signal is at a first signal level. a second output signal from the other output terminal of the flip-flop, the clock signal, and the asynchronous binary signal as input, and when the asynchronous binary signal is at the second signal level, the clock signal is input. a second AND circuit, one input terminal is connected to the output terminal of the second AND circuit, the other input terminal is connected to the output terminal of the first AND circuit, and the output terminal is connected to the output terminal of the first AND circuit; A synchronous circuit comprising an OR circuit connected to a clock input terminal of a flip-flop.