JPS59194230A - Input and output controller - Google Patents

Abstract

PURPOSE:To allow an input and output device to read and write data from in a main storage device by the desired number of times by providing a means, etc., for counting a signal which indicates that the input and output device obtains the right to read and write data from in the storage device. CONSTITUTION:The means for counting the signal which indicates that the input and output device obtains the right to read and write data from in the storage device within a specific time is provided. For example, when an initial signal 26 is supplied from a CPU, etc., the output signal 13 of an OR gate 9 is turned on, and a timer 1 is started to turn on a signal 15 and turn off a signal 14 while resetting a counter 2. Then, the counter 2 starts counting frequency that a bus release signal 12 outputted from a CPU, and a register 3 holds the permissible value of the frequency of access from the input and output device set through the CPU to the storage device. A comparator 4 compares a signal B from the counter 2 with a signal A from the register 3, and when B<A, a CPU stop signal 19 is turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic computer/
Regarding the stem.

The conventional direct memory access method (DMA) is
A method that enables DMA only when the main processing unit (hereinafter abbreviated as CPU) is not using the main memory, the so-called cycle steal method, and a method that frees up the main memory by stopping the CPU and enables DMA. A so-called burst method, and a method that enables one DMA transfer each time the CPU executes one instruction have been adopted.

However, it has not been possible to control the ratio between the time the CPU takes to read/write to the main memory and the time the input/output device takes to read/write to the main memory. Therefore,
The Hitodeba device was not always able to access the main memory as many times as necessary.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an input/output control device that allows an input/output device to read/write to/from a main memory a desired number of times.

According to the present invention, in a device having a storage device, a CPU that reads/writes to the storage device, and an input/output device that reads/writes the storage device without depending on the control of the CPU, so-called direct memory access, a counter that counts a signal indicating that the input/output device has obtained the right to read/write the storage device within a predetermined time; and a CPU.
A register whose allowable number of accesses is set by
It has a comparator that compares the counter value and the register value,
If the comparator determines that the value counted by the counter at a predetermined time is smaller than the value set in the register, a signal is sent to the processing unit to release the right to read/write. An input/output control device is obtained which is characterized in that it transmits data.

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

In the drawing, a signal 26 is an initial signal for starting the circuit of this embodiment, and is given from a CPU 27 or another device. When the signal 26 turns on, the OR gate 9
The output of signal 13 is turned on. The signal 13 is connected to the start terminal of the timer 1 and the reset terminal of the counter 2, and the signal 15 indicating that the timer 2 is in operation is turned on, and the signal 14''f indicating that the operation of the timer 2 is finished is turned off.
Reset counter 2. The signal 15 is connected to the count enable terminal of the counter 2, and when the signal 15 is turned on, the counter 2 outputs l from the CPU 27.
Start counting the number of times the bus release signal 12 turns on.

The register 3 is connected to the CPU 27 via an address bus 22 and a data bus 23, and holds an allowable number of accesses to the storage device of the input/output device set by the CPU 27. The output signal 24 of the counter 2 and the output signal 25 of the register 3 become the input signals B and A of the comparator 40, respectively.
Depending on the comparison result, the comparator 4 turns on either the signal 17 indicating that A) is B or the signal 18 indicating that A≦B, and turns off the other.O Timer 1 is predetermined. When the operation end signal 14 is turned on after counting the time, the signal 17 is turned on, that is, if the value of the counter 2 is smaller than the value of the register 3, both input signals of the AND gate 11 are turned on. Logic gate 11 is CPU
Turn on the stop signal 19. When signal 18 is on, that is, when the value of counter 2 is larger than the value of register 3,
Since both inputs of the AND gate 8 are turned on, the output signal 13 of the OR gate 9 is not turned on, leaving this circuit in the same state as it was immediately after starting.

When the signal 17 turns on, the CPU stop signal 19
As described above, when the CPU stop signal 19 is turned on, the CPU releases the address bus 22 and the data bus 23, so the bus release signal 12 is turned on periodically.

This state continues until the value of the register 3 and the value of the counter 2 become equal, and as the signal 17 is turned off, the CPU stop signal 19 is turned off and the CPU 27 resumes operation. The switching of the CPU stop signal from on to off is detected by the flip-flops 5 and 6 and the AND gate 7, and is input to the OR gate 9, returning the circuit to the state immediately after starting.

In order to prevent this circuit from substantially affecting the CPU 27, it is sufficient to set the register 3 to 0.

As explained above, the present invention controls the read/write ratio of the main memory of the CPU and input/output devices, and adjusts the processing power of the CPU and input/output devices to an appropriate ratio, thereby increasing the processing capacity of the entire system. It has the effect of improving.

[Brief explanation of the drawing]

The drawings are diagrams showing one embodiment of the present invention. 1...Timer, 2...Gun/Counter, 3...
...Register, 4...Comparator, 5,6...
... 7 ritz 70 knobs, 7° 8.11... logical product game), 9,10... logical sum gate, 12...
...Bus release signal, 22...Dan Atrea, Ha.
x4.23...Data bus, 27...Dan/cP
U.

Claims (1)

[Claims] In a system that includes a storage device, a processing device that reads/writes to the storage device, and an input/output device that exchanges data with the storage device by memory access, within a predetermined time. a counter for counting the number of times the input/output device has accessed the storage device; and a register in which a permissible number of accesses of the input/output device to the storage device is set to 11 by the processing device;
a comparator that compares the value of the counter and the value of the register, and when the comparator determines that the value counted by the counter is smaller than the value set in the register; (1) An input/output control device that prohibits access of the processing device to the storage device.