JPS59168675A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MOS transistor suitable for formation in high density of a large-scale integrated circuit having no deterioration of the characteristic by reducing resistance, by contriving to smooth shallow junction and the completed surface, and moreover by thickening a field oxide film by a method wherein a source region and a drain region are formed comparatively thick according to selectively grown layers formed on a substrate. CONSTITUTION:After a field insulating film 2 is adhered to be formed on the main surface of a semiconductor substrate 1, an opening part 3 is formed at an MOS transistor forming part according to selective etching. Then a passivation film 13 consisting of SiN, etc. is formed on the substrate 1 corresponding to a gate part in the opening part 3 thereof. Then epitaxial layers 9, 10 are selectively grown respectively in the opening part 3 between the passivation film 13 and the field insulating film 2, and the layers 9, 10 thereof are made as a source region and a drain region. Then after the whole is oxidized, the passivation film 13 on the gate part is removed, then a gate insulating film 4 is formed on the substrate 1 corresponding to the gate part, a gate material film 5 is adhered to be formed, patterning is performed to form the gate part 7, and an aiming MOS transistor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices, particularly MOS devices suitable for 1t1J densification.
The present invention relates to a method for manufacturing a transistor.

Background technology and its problems In order to increase the density of large-scale built-up circuits (1, 31),
Conditions such as reducing the dimensions of the element in the horizontal and vertical directions and smoothing the element surface are required. Specifically, methods for forming shallow junctions, new isolation techniques between elements, etc. are being developed. However, if we try to make the junction shallower in a MOS transistor, sieving f & resistance of the source and drain etc. becomes a problem, and if we try to make the field insulating film etc. thinner to make the element surface flat, The problem was the increase in capacity.

Purpose of the Invention The present invention solves the two problems and proposes a manufacturing method for MO3L transistors suitable for high density. (It is something to do.

SUMMARY OF THE INVENTION The present invention provides a step of forming a first insulator having an opening on a semiconductor substrate, a step of forming an insulator in the opening, and a step of forming an insulator in the opening in the substrate.
a step of forming an insulating layer, a gate, at least a gate 1-
The method includes a step of forming a third insulating layer on the side surface of the semiconductor device, and a step of forming a semiconductor I- between the first and third insulating layers to serve as source and drain regions, respectively.

According to this invention, it is easy to reduce the resistance of the source and drain, and at the same time, the junction can be made shallow. Also, the surface is extremely smooth.

Example Next, embodiments of the present invention will be described using the drawings.

FIG. 1 shows an embodiment of the invention.

First, as shown in FIG.
A field insulating film (2) of a predetermined thickness is formed by etching the insulating film (2), and selective etching is performed on this insulating film (2) to form an opening (3) in a portion where a Mos transistor is to be formed.
) to form.

Next, in the opening (3), there is a gate insulator (4), a cathode material film (corresponding to an electrode) (5), and a gate material film (5).
) is successively formed with a passivation film (6) and selectively etched to form a so-called gate part (7) as shown in FIG. 1B.
) to form. The gate insulating film (4) is, for example, 5102
+SiN etc. can be used. The gate material film (5) can be made of polycrystalline silicon, ganide, metal, or the like. In particular, when polycrystalline silicon is used as the gate material film (5), impurity doping is performed by using polycrystalline silicon containing impurities, by diffusion or ion implantation from a 5-hot impurity containing impurities, or by a combination of these. It is possible to do things like this. The passivation film (6) may be made of SiN +5i02 or the like.

Next, the entire surface is thermally oxidized or CVD (chemical vapor deposition)
After forming an insulating film (8) of -C, for example, 5I02+StN or oxygen-containing polycrystalline silicon, etc., by anisotropic etching, such as ion milling, as shown in Figure 1C, At least gate material film (5)
An insulating film (8) is left on the side surface of the insulating film (8).

Next, as shown in the first diagram, epitaxial layers (9) and θ0) are selectively grown in the openings (3) on both sides sandwiching the gate portion (7). These layers (9) and αO) are used as a source region and a drain region of the second conductivity type, respectively. Selective epitaxial layer (91, IJω is 5iH4-1-llC
The growth is performed by using a gas such as 1-based or 5iH2CI2 + HCi-based gas. At this time, polycrystalline silicon may be selectively grown by controlling the growth conditions (temperature, gas flow rate, etc.). Source and drain region (9) and α0)
The doping of the second conductivity type impurity can be carried out simultaneously during selective growth, by diffusion or ion implantation from impurity-containing 5i02 between the first drawing and E steps, or by a combination of these. be able to.

Next, as shown in FIG. 1E, after the entire surface is oxidized, the barrier film (6) on the gate material film (5) is removed by etching. Shallow junctions jz and j2 are formed in the substrate (1) by epitaxial J-shading (9) and 001 impurity diffusion.

Next, a wiring material such as metal or silicide is deposited and buttered, and a gate wiring (11) and source wiring and drain wiring are formed in a wide area (not shown) to achieve the purpose shown in FIG. 1F. MO'S) transistor (12) is formed.

According to this manufacturing method, the source and drain regions (9) and α0) are composed of an epitaxial layer or a polycrystalline silicon layer that is selectively grown on the substrate. It becomes easy to reduce the resistance of the source and the drain, and at the same time, the junction between the source and the drain in the substrate (1) can be made shallow. The resulting surface is also extremely smooth without making the field insulation III+21 thinner. Since the gate channel portion is formed directly on the substrate (1), it is not affected by the characteristics of the selectively grown layer. Furthermore, since the field insulating film (2) can be formed relatively thick, the capacitance does not increase. In addition, when forming the gate wiring (11), the passivation film (6) is
There is no need to open a new contact window just by removing the contact, and wiring can be immediately formed using metal, silicide, etc., making wiring formation extremely easy. The gate portion, source, and drain regions are formed by so-called self-alignment lines.

FIG. 2 shows another embodiment of the invention.

In this example, as shown in the second figure, a field insulating film (2) is deposited on the main surface of a semiconductor substrate (1), and then an opening ( 3) Form. And this opening (3)
A passivation film (13) made of SiN or the like is formed on the substrate (1) corresponding to a portion of the data 1 in the substrate.

Next, as shown in FIG. 2B, epitaxial layers (91, α0) are selectively grown in the openings (3) between the passivation film (13) and the field insulating film (2).

In this case, a polycrystalline silicon layer can be formed by controlling the growth conditions in the same manner as described above. Let this epitaxial Jtii (9) and θω be a source region and a drain region.

Next, after oxidizing the entire surface as shown in FIG.

Next, in the second diagram, the base fil corresponding to the cage part is shown.
A gate insulator (4) is formed on top, and then a gate material film (
5) is deposited and patterned to form the gate portion (7) to form the desired Mo5t'' run disk.

Also in this manufacturing method, the source and drain regions (9),
Since α0) is composed of a selectively grown layer formed on the substrate (1), it is easy to reduce the resistance of the source and drain, and the junction can be made shallow. The surface is also smoothed.

FIG. 3 shows yet another embodiment of the invention. This example shows an example of a complementary MO3I-Lancistor integrated circuit (IC).

First, as shown in FIG.
For example, an N-type silicon semiconductor substrate (21) is prepared.

This silicon substrate (21) has a higher impurity concentration than a normal complementary MOS transistor IC (for example, a specific resistance of 0.
1Ωcm) can be used.

The base body (21) is a substrate whose main surface is the 0° (100) plane. Then, a P+ type buried region (22) is formed by implanting boron ions or using a boron silicate glass film as a diffusion source in a portion of the soil surface of the base (21) where, for example, an N-channel MO3I transistor is to be formed.

Next, as shown in FIG. 3B, an isolation insulating film (for example, Sj02 film) is formed by thermal oxidation or CVD (23).
After forming, the insulating film (23) in the portion where the Mo3t transistor and diode will be formed is removed by a photoetching process, leaving the insulating film (23) in the field portion.

Next, as shown in Figure 3C, the opening (
24), P type and N shadow regions (25) and (26) having an impurity concentration of, for example, 1Qi4 to 101 bcm-' are formed using selective epitaxial technology and ion implantation technology.

(29) is a photoresist layer that serves as a mask when ion-implanting phosphorus as an N-type impurity. Field part insulation [3 (23) and selective epitaxial growth region (25
) and (26), it can be filled with spin code 5i02 (27). At this time, if you have 1 night and 1 night, N channel name M OS'
Leakage current at the channel end may be a problem with I-transistors, but
By placing 5io2 (27') in the vicinity, a high-concentration region (28) is formed in the adjacent part and C can be eliminated.

Next, as shown in FIG. 3, a P+ source region (31) is formed in the region where a P channel Mos transistor is to be formed.
and Train Territory II! 1 (32), and an N+ source region (33) and drain region (34) are formed in the region where the N-channel MO3I- transistor is to be formed.
A gate insulator +1Q (36) is formed on the gate part of the gate, and a gate material film (37) is formed on top of it. In this case, the source region and drain region have a height of 1
It is better not to reach the base body (2I) and the embedded area (22). This is because the breakdown voltage decreases and the junction capacitance increases. (38) and (39) are diodes. In this way, the desired integrated circuit of complementary MOS transistors is obtained.

In this manufacturing method, there is an insulating film (23) between each transistor.

Separated by high concentration substrate (21) and buried region (22) -
Since there is C, malfunctions due to latching are less likely to occur.

Further, since there is no problem with bird's beak or channel stopper site diffusion caused by conventional selective oxidation, high integration is possible.

Effects of the Invention According to the present invention as described above, since the source region and the drain region are formed of selectively grown layers formed on the substrate, the resistance can be reduced by forming them relatively thick. At the same time, shallow joints can be easily obtained. Also, the cracked surface is extremely smoothed. Further, since the field oxide film can be formed relatively thick, an increase in capacitance is not a problem. Therefore, a Mos+- transistor suitable for increasing the density of large-scale integrated circuits can be obtained without deteriorating the characteristics.

[Brief explanation of the drawing]

Figures 1A-F are cross-sectional views showing one embodiment of the present invention in the order of steps, and Figure 2A-1) shows other embodiments of the present invention.
FIGS. 3A to 3D are cross-sectional views showing still another embodiment of the present invention in the order of steps. (1) is a semiconductor substrate, (2) is an insulating film, (3) is an opening 1, (4) is a case I-insulating film, (5) is a gate material film, (9) is a source region, 00) is the drain region. 1st tsubo

Claims (1)

[Claims] a step of forming a first insulating layer having an opening on the entire surface of the semiconductor substrate; a step of sequentially forming a second insulating layer, a first insulating layer, on the substrate in the opening; and at least A method for manufacturing a semiconductor device comprising the steps of: forming a third insulating layer on a side surface of the insulating layer; and forming a semiconductor layer between the first and third insulating layers to form a source region and a drain region, respectively.