JPS59121552A - System for detecting failure - Google Patents

Abstract

PURPOSE:To detect automatically a failure of a register by the firmware or hardware without requiring the operator by comparing a data stored in the register and the inversion of each bit of the data. CONSTITUTION:A transferred data is inputted from a terminal A of a multiplexer 20 and fed to registers 1, 6 and 11 and one of the data in the registers is selected by an output of AND circuits 2, 7 and 12. Suppose that the register 1 is selected, after the data is stored in the register 1, it is read and when an error is detected by a parity error detecting circuit 5, an error signal is transmitted to OR circuits 3, 17. The signal through the OR circuit 3 is fed to the circuit 2, which makes the register 1 enable, and the signal fed to the circuit 17 makes a register 22 enable via an AND circuit 19. Further, the data from the register 1 is stored in the register 22 via a multiplexer 16. Moreover, each bit of the data is inverted by an NOT circuit 21, the result enters the register 1 by switching operation of the multiplexer 20, and the inverted data enters a comparison circuit 23 via the multiplexer 16 and compared.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a data transfer device that includes a plurality of registers and transfers data including parity pits.

In particular, the present invention relates to a fault detection method that automatically detects faults in the plurality of registers.

(b) Prior Art and Problems In a data transfer device that is equipped with a plurality of registers and transfers data including parity bits, if a failure in the plurality of registers occurs, each bit of data stored in the registers is read out,
Detection can be performed by inverting each bit of the data and storing it in the register again, reading it out again, and comparing it. However, the conventional method has the disadvantage that the above operation must be performed manually.

(C) Object of the Invention In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a fault detection method that automatically detects register faults by firmware or hardware without human intervention.

(d) Configuration of the Invention The configuration of the present invention includes a parity error detection circuit and a parity error signal detected by the parity error detection circuit in a data transfer device that includes a plurality of registers and transfers data including a parity pinpoint. a circuit for inverting each pin of the data; and a circuit for comparing each bit of the data with each pin 1- inverted by the circuit for inverting each bit of the data. This is designed to detect register failures.

(e) Examples of the invention The present invention uses data stored in registers.

Compare each bit of the data with the inverted version of 7 bits.

If there is a matching bit among both bits, it is considered that a fault has occurred in the register location corresponding to that bit. Utilizing this fact, the process from parity error detection to finding the faulty bit is performed. The operations can be performed automatically using Bar i-Ware.

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention. The transferred data enters from terminal A, passes through multiplexer 20, and is sent to a plurality of registers 1, 6, and 11. Register addresses input from terminal E are OR circuits 3 and 8.
．． The AND circuit 2, 7.12 performs an AND operation using the clock input from the 1st terminal via i3, and selects one of the registers 1, 6.11. For example, assume that register 1 is selected. The operation is the same even if the other register 6 or 11 is selected. When register 1 is selected, the data sent from multiplexer 20 is transferred to register I.
G, it will be stored. The data read from register 1 undergoes a parity check by parity error detection circuit 5. If a parity error is detected here, a parity error signal is sent to OR circuits 3 and 17, and the parity error signal sent to AND circuit 2 via OR circuit 3 enables register 1. Further, the parity error signal sent to the OR circuit 17 is ANDed with the clock by the AND circuit 19, and the register 22 is enabled. On the other hand, data read from register 1 is sent to terminal B via multiplexer 16.

The data is stored in register 22. Also at the same time NOT
Each bit of the data is inverted by circuit 21, and multiplexer 20 switches the circuit and sends it to register l, and since register l is enabled, the inverted data is stored in register l. The inverted data is read out again, passes through the multiplexer 16, enters the comparison circuit 23, and is compared with the data in the register 22. If there is a matching focus here, the occurrence of a failure in register 1 is reported from terminal C.

FIG. 2 is a block diagram of a circuit showing another embodiment of the invention. In this embodiment, a mode signal is provided, and by operating this circuit after a retry performed by parity error detection under firmware or hardware control, it is possible to automatically distinguish between an intermittent failure and a fixed failure. This is what I did.

As explained in FIG. 1, when a parity error is detected from the data stored in register 1 and read out in register 2, a retry is performed. Since no mode signal is applied from terminal F during this retry execution, AND circuit 4 blocks the parity error signal. Also, since the parity error signal sent to the OR circuit 17 is blocked by the A N D circuit 18, the register 22 remains disabled. If the above retry is not successful, a mode signal is sent from the 1st terminal F and the AND
Circuit 4. ．． Enter 9.14. AND circuit 4 performs an AND operation between the mode signal and the parity error signal.

OR circuit 3. Register 1 is enabled via AND circuit 2. Also, AND circuit 18 is turned on, and AND circuit 1
9, the register 22 is enabled and the data from the register 1 is stored. The subsequent operations are the same as in FIG.

(f) Detailed Description of the Invention As described above, the present invention can automatically detect failures in registers without manual intervention, so failures can be discovered quickly and accurately. Furthermore, the embodiment shown in FIG. 2 can determine whether the fault detected by the mode signal is a fixed fault or an intermittent fault.
Failure handling and maintenance can be easily performed quickly and accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the invention, and FIG. 2 is a block diagram of a circuit showing another embodiment of the invention. 1.6 and 11.22 are registers, 16.20 is a multiplexer, and 23 is a comparison circuit.

Claims (1)

[Claims] In a data transfer device that includes a plurality of registers and transfers data including parity bits, a parity error detection circuit, a register operated by a parity error signal detected by the parity error detection circuit, and each of the data A circuit for inverting bits and a circuit for comparing each bit of the data with each bit inverted by the circuit for inverting each bit of the data is provided, and a failure of a plurality of registers is detected. Fault detection method.