JPS59129434A - Integrated circuit element with test circuit - Google Patents

Abstract

PURPOSE:To prevent the increase in number of terminals of the IC element with a test circuit by a method wherein a terminal and a circuit to be used for switching of output mode are added, thereby enabling to perform a switching to test or IC output by a switching signal. CONSTITUTION:The two-bit input signal Vmt of terminals 35m1 and 35m2 is decoded 36 in a test circuit 32, the buffer 37 (371-374) and 38 (381-384) group, which are OR-connected in test condition, are controlled by the outputs Q1-Q4 in the test circuit 32, and it output information Dt1-Dt4 of the corresponding test mode and clock CLt1-CLt4. If the input signal Vm0 to be sent to a terminal 35m0 is ''1'', for example, the output selectors 331 and 332 turn out output from terminals 3501 and 3502. When CLt is added to the clock terminal of a shift register, serial information can be read easily. If Vm0 is ''0'', the selector is switched to LSI 31, and its information is outputted. Said information is the control signal such as the request for information and the like, the Dt1-Dt4 are the serial information for index, ROM read-out information for reproduction and the like, and CLt1 corresponding to Dt1. According to this constitution, the terminals for testing can not become excessive.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an integrated circuit device with a test circuit in which a large-scale integrated circuit such as a speech synthesis circuit and its test circuit are housed in the same package.

[Background technology]

Generally, when testing the operation of a large-scale integrated circuit such as a speech synthesis circuit using an external circuit, it is a very complicated task. Conventionally, devices with a built-in test circuit have been considered, but the addition of the test circuit increases the number of test terminals, resulting in an inconvenience that the total number of terminals becomes too large.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to reduce the increase in the number of terminals due to the built-in test circuit.

[Disclosure of the invention]

(Configuration) Figure 1 shows the configuration of the present invention, in which OL) is a large-scale integrated circuit such as a speech synthesis circuit, and each logic circuit (8
1aX81b)..., human serial data (Da) (Db)... is the data (
Da) (Db)
a) (CLb) . . . is processed based on the following. (The three smells are each logic circuit (81a) (82b)
Test circuit for checking the operating status of ・・・・・・-・(88t) (88g) is the output switching circuit, (85mo
) Fi output/output-do switching terminal, (aso+) (ssng
) is the output terminal, which connects the integrated circuit (31) and the test circuit (
) and the output switching circuit (8B+) (8B□>Vi are housed in the same package; (foundation). Here, the output switching circuit (881) (88□)
Based on the 7-mode switching signal (Vmo) input to the output terminal (85111) (8511), the data (Dt) and output terminal (CLt) are output from the test circuit. or integrated circuits (31
) is designed to switch between outputting the output terminal (loo+) (Dnt) of the integrated circuit fil.
85n+) (85oz) is used to output the output data (Dt) and output data (CLt) from the test circuit, so the increase in the number of terminals due to the built-in test circuit 2 is reduced. ing. In addition, since the pit serial data (Dt) and the corresponding zero (CLt) are output from the test circuit, the shift register can be used without using an external zero. The digit (Dt) mentioned above can be easily read.

(Embodiment) Figures 2 to 7 show an embodiment of the present invention, in which the PARCOR type voice synthesis circuit of the test circuit material,
PARCOR type speech synthesis right speech synthesis method is explained.

The amplitude parameter (hereinafter referred to as the A parameter) that represents the magnitude of the sound by sampling the audio signal with a sampling pulse having a frequency higher than the audio frequency, and the pitch parameter (hereinafter referred to as the P parameter) that represents the pitch or fundamental period of the sound. ) and spectral parameters (hereinafter abbreviated as S-parameters) representing the timbre of the sound, that is, the spectral distribution, are extracted and stored in a data memory, and the feature parameters read from the data memory are The PARCOR type speech synthesis method, which is a type of speech synthesis method that synthesizes the original speech signal based on Sampled sample values Xt and Xt
The PARCOR coefficient (partial autocorrelation coefficient: below, the parameters are This method synthesizes speech using S-parameters. Here, the K parameter is 1 frame (5M 20m5I!c) where the audio appears to be in an almost steady state.
), the audio signal (Vs) is sampled at appropriate intervals (to) (approximately 100 μE), and the correlation coefficient between adjacent sampler values is set to 1, and the sampler values separated between multiple samples are In between, the influence of the sampled values in between is calculated by linear prediction using the least squares error, and the correlation coefficient obtained by subtracting them is expressed as -Kil
1. The parameters for this are K2S ~%
The coefficients representing the partial autocorrelation with points close to Xt, such as Kl, contain a wealth of information regarding the spectral distribution, but the coefficients representing the partial autocorrelation with points far from Xt, such as K3, K, , K, o, Since the autocorrelation coefficient does not contain much information about the spectral distribution, the number of pits can be reduced by assigning a large number of quantization hits to low-order parameters and a small number of quantization hits to high-order parameters. It is more effective to reduce redundancy by reducing Therefore, the PARCOR method has a better band compression rate than the autocorrelation coefficient method, which uses autocorrelation coefficients as S parameters and assigns the same number of hits to each coefficient. %, the parameters are compressed and stored or transmitted for each A, P, 5 pits for the A parameter, 6 pits for the P parameter, 6 pits for each coefficient of the K parameter, K,...K111. 7.6.5.
4.4.4.8.8.8.8 human etc.

The configuration of one embodiment of the present invention will be described below with reference to the illustrated embodiment. FIG. 4 is a block diagram of a speech synthesis circuit according to the present invention. As shown in the figure, this audio system is comprised of a control IC (A) including a data storage section (8), an integrated circuit for audio synthesis (31), and an output circuit (B). , data is exchanged pit-serially between onton and tsuji. All voice characteristic parameters are stored as 10 pit data in the reproduction ROM fl). The number of data assigned to each feature parameter is optimally distributed according to the degree to which the feature parameter contributes to sound quality. Figure 5 shows the playback ROM (
1) The number of data of each feature parameter is shown in the boxes hksP, KIO~ stored in . For example, in the case of the A parameter, 82 pieces of data expressed by 10 hits are stored. Therefore, the number of hits of the relative address required when accessing arbitrary data of the A parameter is Fi5 pits. Since this relative address is expressed by compressing the feature parameters to the minimum necessary, it is called compressed parameter 7. On the other hand, playback ROM
The actual feature parameters stored in fl) are called playback parameters. As is clear from the above, the reproduction parameter number of hits 1d, A, P,
The number of pits in the compression parameter is 10 pits in common for each characteristic parameter of Kin"K+, but the number of pits of the compression parameter is different for each parameter of A, P%, and +o"K1, and is 5.6.8.3.8, respectively. .8.4.
4.4.5.6.7 (58 total).

In addition, there is 8 data as a reserve area.
A portion for each is reserved in the playback ROM. Such a compression parameter is 2°m, which allows the audio signal to be considered to be in an approximately steady state.
Since one set (=58 pits) is extracted for each trial (1 frame), it is possible to record audio signals at a rate of at most 2650 hits/second, and when silent sections and beat sections are taken into account, the actual :f: It is capable of recording audio signals at approximately 1600 pits/second.

Such compression parameters (i.e. playback ROM +
1) is read out from the data storage section (8) and sent through the switching circuit (10) every l frame.
"The data is stored pit serially in the link register (3), but since it is not possible to retrieve the stored data from the playback ROM (fl) using only such a relative address, the data is stored in the index ROM +21 as shown in Figure 6. As shown, the stored start addresses are taken out one after another under the control of the address counter (II) and added to the above-mentioned relative address by the addition circuit (4), thereby obtaining the absolute address (9) of the playback ROM fl). The playback ROM fl) is accessed using the absolute address.Hereinafter, the playback ROM fl
) will be described in detail. The index ROM +21 stores the compression parameter hit distribution number as an 8-pit binary number, and the playback ROM +1+ has one pit for common use to reduce the storage capacity. +
A reserve hit corresponding to the reserve area within 1+ is provided. Data regarding the number of pit allocations for compression parameters is sent to the reproduction control circuit (12), and the reproduction control circuit 02) shifts the shift clock by the number of pit allocations to the link register (3).
).

Therefore, from the ring register (3), for example, in the case of A parameter, 5 pits,
Compression parameters (relative addresses) are serially sent to the adder circuit in the following order: 6 hits for the P parameter, 8 hits for I/i for the K1° parameter, 7 hits for the Kl parameter, etc. It is. The link register (3) is composed of three shift registers so as to occupy as little chip area as possible. In addition, the leading address in the playback ROM fl) of each feature parameter stored in the index ROM (2) is sequentially sent one hit at a time to the addition circuit (4) via the parallel-serial conversion circuit (13). Therefore, the absolute address is calculated by sequentially adding each hit one by one. The absolute address consisting of the serial data calculated in this way is
) is converted into parallel data via the ROMf for playback.
ll can be accessed.

By the way, the feature parameters output from the playback ROM +1+ are updated every frame,
If the feature parameters change discontinuously at the connection points between each frame when updating data, the audio signal may be distorted and the clarity may deteriorate. An interpolation calculation circuit (5) is provided to perform approximate linear interpolation at eight points within one frame. This interpolation calculation circuit (6) is controlled by a timing control circuit (c), which calculates eight interpolation calculation circuits in one frame (20 msec) in the case of two barrels, as shown in Fig. 8.
(2.5m sec), and 25 parameter reading P-o-tsuku (100t) are generated during one D-O-tsuk.
ttec), and furthermore, 22 pit reading T registers (4.5 μs! lc) are created in one P register. Data is read into the ring register (3) at the first Dl among the eight D0's. Each compression parameter A.

P, to. . . . are sequentially read in the K1 odd-numbered P/)Ots, for example, Ts-T in the A parameter FiP1 section. 05 T clocks. Even numbered P 0 tsuku or T other than the above
The input circuit is used as a connector for the interpolation calculation circuit (6), the sound source ROM+61, the digital filter (7), etc. 2. by the interpolation calculation circuit (6).
Each feature parameter updated to a new value every 5H1sec is connected to a P latch (16) and an AK latch (23).
) is temporarily stored. However, all parameters that are not needed for the time being for interpolation calculation are transferred to the AK parameter stack (24) and stored as data for speech synthesis in the digital filter (7). On the other hand, the data regarding the fundamental period of the voice stored in the P latch (16), that is, the P parameter, is preset to the preset type subtraction link (17). The 0 count of this subtraction counter (I7) has the same frequency as the sampling pulse, and the 0 output signal (VR) of this subtraction counter (17) causes the sound source RO to
The address link (18) of M+61 is reset, and the sound source control data is sequentially read out from the sound source ROM (6) at a basic period corresponding to the period of the 0 output signal (VR) of the 1-subtraction link θη, and the basic period is The voiced sound source (19) is driven using the sound source control data to generate a voiced sound having a fundamental period. Note that the above sound source control data is data for faithfully reproducing the tone by reproducing the residual waveform obtained by frequency analysis of the original sound.

On the other hand, if the sound has no fundamental period, the sound source control circuit (
The switching circuit (4) is driven and switched to the unvoiced sound source ff11.The unvoiced sound source (21+l'i) generates white noise without a fundamental period.

Next, the A parameter and the 2 parameter are supplied to a digital filter (7), which reproduces the sound by adding information regarding amplitude magnitude and spectral distribution to the signal supplied from the sound source circuit. In FIG. 4, (9) is a code detection circuit, (2I51 is an amplifier, □□□ is a speaker, and η is a crystal oscillation circuit.

By the way, as shown in FIG. 7, the test circuit (32 is a decoding circuit for decoding two test mode switching signals (Vmt) inputted to the test mode switching terminals (85ml) (85mg)) and a decoding circuit for Output (Q,
) to (Q, ), and the outputs are tied-ORed tri-state buffers (871) to (874),
(88t) to (884), and data (Dts) and data corresponding to each test mode set by the test mode switching signal (vmt).
(CLt+) ” (cLt4) is the test circuit (2
) output data (Dt), ri0tsuk (CLt)
is output as For example, test mode switching signal (vm
When t) is (o, on), the output (Ql) of the decoding circuit (36) becomes "H# level" and only the tri-state buffers (87+) (88+) operate, and the data (Db)
and ri0tsu (CLt+) are output from the test circuit (c). Here, the output mode switching signal (VmO) input to the output upper mode switching terminal (asmo) is
In this case, an output switching circuit (sat
) (a8g) is switched to the test circuit (32 side), so the data (Dt+) is output to the output terminal (35o+), and the data (CLt) is output to the output terminal (85o+).This output Input the data (Dt+) output to the terminal (85o1) to the data terminal of the shift register,
Output terminal (output at 850 or 0 (Cut))
Serial data (Dt+) can be easily read into the shift register by applying Dt+ to the shift register's output terminal.

On the other hand, when the output mode switching signal (Vm o) is 0#,
Output switching circuit (88υ (88υ) Vi integrated circuit (31)
integrated circuit (31) output data (Vo+
) (Vox,) is the output terminal (85o+) (85o
g).

Note that the output data (VOI) (VOI) of the integrated circuit @1)
I)... are control signals such as data request signals and ready signals, and test circuit data (Dt+)'' (Dt4) is the index ROM (2
Read data from 1, adder circuit (4) output, RO for reproduction
Serial data such as read data of Mfl) is used, and clocks (CL1+) to (CLtθ are clocks corresponding to the data (Dt+) to (Dtυ), respectively.

(Embodiment 2) Fig. 8 shows a circuit diagram of the main part of another embodiment. , an address counter @9) with a self-increment function that counts a predetermined number of times 0, □ is provided, and the data (playback parameters) in the playback ROM (1) are continuously read based on the output of the address counter (39). The contents of the playback ROM (1), which stores a large amount of data, can be read quickly.

[Effect of invention]

As described above, the present invention provides an integrated circuit element with a test circuit in which an integrated circuit and a test circuit for the integrated circuit are housed in the same package, in which an output mode switching terminal is provided, and an input signal is input to the output mode switching terminal. An output switching circuit is provided that switches between outputting the test circuit output or the integrated circuit output to the output terminal based on the output mode switching signal, so there is no need to provide a new output terminal for the test circuit, and the test There is an advantage that the increase in the number of terminals due to the built-in circuit can be reduced, and when the integrated circuit is formed to process pit-serial data, the above-mentioned hit-serial data can be used as the test circuit output. By outputting a 0x♂ corresponding to the data, the data can be easily read using a shift register.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of the present invention, Fig. 2 is an explanatory diagram of the principle of a speech synthesis method according to an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of the same, and Fig. 4 is a block diagram of the same as the above. , FIG. 5 and FIG. 6 are diagrams showing the configurations of the reproduction ROM and index ROM same as the above, FIG. 7 is a circuit diagram of the main part of the same, and FIG. 8 is a main part circuit diagram of another embodiment of the same. be. 01) is an integrated circuit, 32/'i test circuit, (88 pieces)
(88g) is the output switching circuit, (34J is the package, (
(85mo) is the output mode switching terminal, (85o+) (85
゜, ) are output terminals. Agent Patent Attorney Ishi 1) Chief 1st Button Vm. Figure 7 35m1 35m2vm' 35mo Vm. 32<-1111 1 71 CLt+
Dt+1 382 l 37゜(1Dt
z 383 ” 73 IDt3 1 JP-A-59-129434 (8) Fig. 8

Claims (2)

[Claims] (1) In an integrated circuit device with a test circuit in which an integrated circuit and a test circuit for the integrated circuit are housed in the same package, an output t-tod switching terminal is provided, and the output
An integrated circuit device with a test circuit comprising an output switching circuit that switches between outputting a test circuit output or an integrated circuit output to an output terminal based on an output mode switching signal input to the mode switching terminal. (2) The integrated circuit is formed to process serial data, and outputs the serial data and a signal corresponding to the data as a test circuit output. An integrated circuit device with a test circuit according to item 1.