JPS5912674A - Image pickup device - Google Patents

Abstract

PURPOSE:To prevent the deterioration in a signal due to a dark current, by providing a detecting means detecting unnecessary charge stored in a photodiode on a same substrate of a two-dimensional solid-state image pickup device in case of a long time exposure. CONSTITUTION:A dark current detecting region 21 is formed on the same substrate of another region, both regions are in the state of temperature equilibrium and all upper surfaces of the region 21 are covered with a light shield member. A clear gate 7 is provided to each vertical transfer register V.BCCD and charges are discharged to an overflow drain OFD1 and a lead 23 in the lump from all the V.BCCDs. Further, an OFD2 discharging the V.BCCD charge in the dark current detecting region 21 is constituted so as to be extracted externally via a lead 22 separately from the other region OFD1. Thus, the deterioration in a signal due to the dark current in case of a long time exposure is prevented by this constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a solid-state camera that is effective for use in an electronic still camera that captures an image using a solid-state image sensor instead of a silver halide film and records the obtained video signal electronically or magnetically. The present invention relates to an image sensor and an apparatus.

One of the problems that arises when trying to use various solid-state image sensors that have been developed and used for video cameras as they are for electronic still cameras is the shutter function. The major advantage of systems that do not use silver halide films, such as electronic still cameras, is that they do not necessarily require complete light shielding, and at the same time, there is no need for mechanical shutters that can cause vibration and noise. . For this purpose, the image sensor itself needs to have a shutter function, which already includes an overflow drain (OFD) and an overflow control gate (OFD).
FCG) with interline transfer C0D-? It has been confirmed that frame transfer COD satisfies this requirement to some extent.

Among these, the interline transfer CCD with OFD prepares for exposure by discharging unnecessary charge from all the light receiving elements to the QFD at once, and also discharges the signal charge generated by exposure to the light-shielded vertical transfer CCD at once. Since the exposure can be completed by transferring the image, it can be said to have an ideal shutter function, and in principle, a shutter time of several microseconds, which could not be achieved with conventional mechanical shutters, is also possible. On the other hand, in the case of a frame transfer CCD, the transfer from the light receiving area to the storage area is performed under exposure, so in principle, as long as the shutter function of the CCD itself is used, a temporary drop in S/N due to high-speed shutter cannot be avoided. , the practical limit is considered to be about 11,500 seconds.

As described above, when using the shutter function of the solid-state image sensor itself, the high-speed shutter side has satisfactory performance, but some problems still remain with the low-speed shutter side.

The main cause of this is dark current, which is a factor that significantly degrades image quality, especially in low-light photography. This dark current has a strong temperature dependence, and becomes smaller as the temperature decreases. Therefore, a method of cooling the image sensor itself to reduce the dark current may also be considered. In this case, the Peltier effect is used as a cooling method, but it requires a large current, increases power consumption, and has many drawbacks such as the time constant until cooling and dew condensation, etc., when incorporating it into a small camera. There is.

It has also been considered to discharge the dark current charges generated in the transfer area during exposure or just before the completion of exposure to the outside, but even this has not been a measure against the dark current generated in the light receiving area.

In addition to cooling the image sensor described above, as a means to compensate for dark current, the light-receiving area corresponding to a part of each horizontal scanning line is shielded from light, and after reading out the signal charge to the outside, the light-shielded area is It has also been common practice in video cameras to remove the dark current component by clamping it to a reference level; In addition to increasing the dark current and narrowing the dynamic range, it also had the disadvantage that the dark current component could not be accurately removed because the dark current of not only the light-receiving area but also the transfer area was added and read out. .

SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional drawbacks, to prevent signal deterioration due to dark current during long exposure, and to provide an effective imaging device for use in electronic still cameras that enables a slow shutter function. This is what we are trying to provide.

The apparatus according to the present invention uses a two-dimensional solid-state image sensor having an electronic shutter function on the same substrate during long-time exposure.
One feature is that a detection means is provided to detect unnecessary charges accumulated in the photodiode.

FIG. 1 is an overall conceptual diagram showing an example of a solid-state imaging device according to the present invention, FIG. 2 is a sectional view taken along line II--II in FIG. 1, and FIG. 3 is a sectional view taken along line 1ll-Ill in FIG.

In these figures, H and BCOD are transfer locks φH
horizontal transfer register to which II+φH2 is applied,
V,, BCCD is transfer lock φvl+ φv2+φ
v3φv4 (in Figures 2 and 6, these are summarized as φV
) is applied to the vertical transfer register. 1
is an overflow drain (OF) for discharging unnecessary charges.
D), 2 is a PN junction photodiode for light reception, and a plurality of them are arranged in a matrix. 3 is OF I)
An overflow control gate (OFCG) formed between the photodiode 1 and the photodiode 2 controls the discharge of the charge accumulated in the photodiode 2 to 0FDI. V, BCCD is a buried channel 4 in the N-type region
and an electrode 5 to which a transfer lock φV is applied, and transfers signal charges in a direction perpendicular to the paper (in the case of FIG. 2) (vertical transfer). 6 is photodiode 2 and V.

With the transfer gate formed between BCCD,
Transfer of signal charges from the photodiode 2 to the V and BCCD side is performed by the required voltage TG applied here. 7 is responsible for the next vertical line adjacent to V, BCOD 0FD1 and V, B CCD embedded channel 4
0FDI from buried channel 4 by the signal CG applied here.
Via V.

The charge of the BCCD can be discharged to the outside of the device. Reference numeral 9 denotes a light shielding member, which here covers the entire area except for the area of the photodiode 2 (although it basically covers the V, BCCD, and V formed by the buried channel 4 and the electrode 5).
It is only necessary to cover this area.

In FIG. 1, a region 21 surrounded by a broken line (a cross-sectional view of this region is shown in FIG. 6) constitutes a dark current detection region, and is formed on the same substrate as the other regions. The region is in a temperature-equivalent state, and its structure is the same as the cross-sectional view shown in FIG. 2 except that the entire upper part of the region 21 is covered with a light shielding member 19. That is, 11 is OFD+
, 12 is a photodiode, 16 is 0FCG, 14
is V.

BCCD buried channel area, 15 is V.

Transfer electrode of BCCD, 16 is transfer gate, 1
7 is a clear gate for discharging the charge of V and BCCD to 0FD218.

In the device configured in this way, a clear gate 7 is provided for each V and BCCD, and all V and BCCD are provided with a clear gate 7.

Charge is transferred from BCCD to OFD I and lead wire 2.
6 side and the dark current detection area 21,
This differs from conventional interline transfer CCDs in that OFD2, which discharges V and RCCD charges, is configured to be separated from 0FDI in other areas and taken out to the outside via a lead wire 22. .

FIG. 4 is a configuration diagram showing an example of a peripheral circuit when the solid-state imaging device according to the present invention shown in FIG. 1 is used in an imaging device for an electronic still camera.

In this figure, 2B is the solid-state image sensor (
(hereinafter simply referred to as COD), and each symbol corresponds to the symbol attached to each terminal in FIG. The reset drain RD, output drain OD, and output gate OG of the output circuit are provided with appropriate DC % voltages VRo, Voo, and VO, respectively.
G is applied. Clock trinos 29 to 65 amplify the output voltages from the analog switches 36 to 43 and connect the terminals CG, CG, CG, and CCD 28 to each other.
,0FCG,RG.

Apply to φI+, φV and TG. When the analog switches 66 to 46 are off, Ot pressure is applied to each terminal of the CCD 28.

Here, the transfer locks φH1e and φH2 of the horizontal transfer register H0BCCD are collectively φH, and the transfer locks φVl of the vertical transfer register V and BCCD.

φV2t φV3t φV4 are collectively referred to as φV. Therefore, there are actually two clock drivers 66 and two analog switches 41, and four clock drivers 34 and four analog switches 42.

44 is a timing pulse generation circuit, which generates pulse groups φCO, φCO2, φ0FCG necessary to drive the CCD 28.
,.

φ0FCG, φRG, φHI, φH2, φVH, φv
2. φv3. In addition to the pulse groups φX and φB supplied to the circuit that performs φv4+φTO and dark current compensation, periodic signals φ5YNC and φ5YNC necessary for video signal processing output from CC028,
A clamp pulse φ'cp, a gate signal φRICCG indicating an effective signal area during recording, and the like are output.

Reference numeral 45 denotes a shutter time calculation circuit which supplies an exposure start instruction pulse φ8T and an exposure completion pulse φED to the timing pulse generation circuit 44 as °C timing signals. Here, the exposure start pulse φ8TART is given by the pusher of the camera shutter button (not shown), and the exposure completion pulse φED is set in the optical system (not shown) based on the photographing condition information such as the aperture value detection resistor 46. This occurs after the shutter time calculated from the output direction of the photometric element by the photometric photodiode 47 thus obtained. Note that although a photodiode 47 for photometry is provided here, the photometry is performed using cc
Photometry may be performed using the D28 itself. In this case, by applying a pan voltage to 0FCG3 and detecting the output currents from all photodiodes 2 in FIG. 2, average photometry over the entire surface can be performed.

48, 49, 50, and 51 are all operational amplifiers, and 56 is a sample-and-hold circuit, which includes a switch element 54, a capacitor 55, and a high input impedance amplifier 56.
It consists of These arithmetic circuits and sample-and-bold circuits constitute a circuit for performing dark current compensation inside the C0D 28.

The first stage operational amplifier 48 applies a bias voltage VOFD to the V of the light-shielded area 21 of the CCD 28 (see FIG. 1) and the oFD 18 provided on the BCCD, and also applies a bias voltage VOFD to the oFD 18 provided on the BCCD. This is a circuit that detects the current ID flowing into the 1F3 and converts it into a voltage, and outputs a voltage e as shown in the equation (υ) to its output 14i.

C6= VOFD + ROe xd-111, (1)
Then, Ro is the value of the feedback resistor (current detection resistor) of the operational amplifier 48, that is, when the dark current charge of C0D28 is accumulated, the analog switch 6 is activated with the pulse φCG.
7 is turned on and voltage Vco is applied, V in region 21
, the l-current it of the BCCD and all the loads -c are simultaneously discharged, a dark current Id flows through the oFD 2, and a voltage eo as shown in equation (1) is obtained at the output end of the operational amplifier 48. I can do it.

The operational amplifier iJ 49 subtracts the bias voltage VOFD from the output voltage eo of the operational amplifier 48, and outputs an output voltage -(R2/R1) Ro-I proportional to the current Id at its output end.
It constitutes a subtraction circuit that obtains d.

One aim of the present invention is to use this dark current proportional output voltage to change the original voltage VTG that should be applied to the transfer gate TG at the time of high-speed shutter, for example. The voltage is subtracted, and the voltage Vtc' resulting from this subtraction is used to control the transfer of signal charges from the photodiode to V and BCOD.

Two operational amplifiers 50, 51 constitute a subtraction circuit for this purpose. The output terminal of the operational amplifier 51 has a voltage e as shown in equation (2). 1 is obtained, and by changing the resistor R4, the coefficient of Id is changed and the effect on the transfer gate voltage is adjusted.

In this example, a linear element is used, but the potential change between the photodiode and V, BCCD due to the transfer gate voltage vto' is non-linear, and this is because a non-linear element is used instead of the resistor R4. This is solved by using

Furthermore, logarithmic compression can be performed by replacing the current detection resistor R with a non-wire circuit including a diode.

The sample-and-hold circuit 53 is provided to cope with a time delay between the timing of current detection by φCGKJ and the timing of charge transfer by φTG.

In this embodiment, there is also an overflow control gate oFCGni+t, two voltages VOFCJl
It is configured to select and use 0FCG2, and this is achieved by turning on either φ0FCG or φQF'CG2.

There is a relationship between the two voltages: VOFCG2 > VOFCGI, and under normal exposure conditions, VOFCGI
is applied to 0FCG, and in this case, when a blooming state occurs and the charge overflows from the photodiode, it can be discharged to the adjacent OFD.

Moreover, when Vgrca2 is applied to 0FCG,
The boundary potential between the photodiode and the OFD is sufficiently low, and all charges existing in the photodiode that are higher than the reference potential are discharged to the OFD.

The operation of the circuit shown in FIG. 4 will be described below with reference to the waveform diagram shown in FIG.

As shown in FIG. 5(,l), when the exposure start pulse φ1ilTART is generated by pressing the shutter button at time t=to, the shutter time calculation circuit 45 uses the pulse φ1ilTART given by the timing control circuit 44 to start shooting. Photometry is started in synchronization with the vertical synchronizing signals V and D shown in FIG. 5(b), and a taillight start instruction pulse φST to the timing control circuit 44 is generated as shown in FIG. 5(e).The pulse φ8T timing control circuit 4
4, φ0FCG2 is set to 〃H''()(high) level as shown in Figure 5(e) and (f) in synchronization with φ8cnd.
By setting φ0FCG+ to Il L tt white, ow ) level, the charge is discharged from the photodiode to the OFD, and the two clear gates φCGI shown in FIG. 5(g)+(').

φCG2 //l("As a level, the charge existing in V, BCCD is also discharged to OF D and OF D2. The above operation can be performed by applying a single pulse, so it is 10μ1le
It is completed in a short time of about e.

Here, the CCD 28 will be explained as being able to be used also as a video camera, and even in the case of still image shooting, it is assumed that the video signal is read out as a field image on a TV.

The vertical synchronizing signals V and D shown in FIG. 5(b) are 1/60
If it occurs continuously with a period of seconds and the exposure is completed within 1/60 seconds from the start of exposure at time t=tl to the next vertical synchronization signal V, l), the influence of dark current is small, and the clamping process for the light-shielded portion does not cause any practical problems.

Figure 5 shows that unlike such high-speed shooting operations, when the shutter time exceeds 1/60 seconds, that is, the exposure does not end even after exceeding 1/60 seconds, and Figure 5 (d)
A case is shown in which the exposure completion signal φED shown in FIG. In such a case, φ is shown in Fig. 5(i).
The pulse indicated by X reaches // L level at time 1 = 12
changes in synchronization with the vertical synchronization signal VD, and the electronic camera shifts to dark current compensation mode.

This pulse φX controls the on/off of the analog switch 570 in the circuit shown in FIG.
If the analog switch 57 is on t, c, then the voltage should be applied to the transfer gate TG (FIG. 5).
The voltage VTG shown in A) becomes VTG=Vto, and complete transfer is realized from the photodiode 2 to V and BCCD. On the other hand, if φX is at //L// level, the analog switch 57 is turned off, and vTG' becomes -CVr according to the dark current Id flowing into OFD2 when the sample-and-hold circuit 5 is in the sample mode.
The voltage is lower than a.

Next, the operation in the vicinity from time t=t3 to t=ts will be explained. After entering the dark current compensation mode, if the exposure completion signal φgD is not generated even after a preset time (for example, 4 cycles 1/15 seconds of ■, ]) has elapsed, at that time t=t3. , two clear gates CGl,
For CG2, the voltage and voltage VCG are applied by generating the voltage pulses φCGI and φCG2, and the dark current charges are discharged from all the sides of V and BCCD. Of these, OF D2
Electric power discharged from agricultural engineering, pulse current and 1r, 4th
The input of the sample-and-hold circuit 56 in the figure is v'rc' from time 1=13 to 1=14 in FIG.
produces a voltage change of In order to memorize and hold this voltage change in the sample-and-hold circuit 5, the pulse φ8 is
= At t4〃], 9th level and oro. Note that this sample-and-hold circuit 56 may be replaced with a peak-hold circuit.

This held voltage VT(1'' is lower than the voltage LEVra, thus resulting in an incomplete transfer from photodiode 2 to V, BCCD, and from time t = j4 while voltage VTG is held) During t=ts, if this voltage is transferred to the transfer gate TG with the pulse φτG shown in FIG.
It becomes possible to transfer only the signal 1E load to the V and T3CCD. At this time, V'rG' is adjusted to an appropriate voltage level according to Id.

Here, it is assumed that there is a certain relationship between the dark current generated in the V and BCCD of the light-shielded area 21 and the dark current generated in the photodiode 2 in the light receiving area.

As a result, 1=1. Only the signal charge generated in the photodiode during the period from t=t4 can be transferred. In this case, it is practical to adjust so that some dark current charge is also transferred to V and BCCD along with the signal charge, and this charge acts as a bias charge to reduce signal charge loss in areas where the signal charge is minute. 1. In addition, this small amount of dark current charge is also transferred to the V and BCCD in the dark current detection area 21, so that it can be removed by clamp processing when reading out from the CCD 28. : Signal charge is transferred from a certain 1° photodiode 2 to V, BCCD, and the remaining dark current charge is transferred again at time 1=1.
e), by changing φ0FCG2 and φ0FCGl shown in (f) and applying voltage voFcG2 to 0FCG, OF
Discharge to D.

゛ After this, the photodiode starts accumulating light-receiving charges again. Further, the time required for the above-mentioned operation is sufficiently short compared to the exposure time from the time t-=tlK to t=t3, and the exposure time error can be practically ignored.

In the timing chart of FIG. 5, 1=1. From t=t8
The operation from t=t3 to 1=15 is almost the same as the operation from t=t3 to 1=15.

In this case, V adjacent to the light receiving photodiode 2
Since the signal charge has already been transferred to , BCCD at t=t4, the charge can no longer be discharged from this v, BCCD, therefore, φCGI is not changed,
A pulse is simply applied to only φCG2, and signal charges are transferred from the photodiode to V and BCCD. V, BCCD during the period from time 1 = t5 to time 1 = 1°
The dark current charge generated in the above can no longer be removed inside the CCD 28, and this is one of the constraints on long-time exposure in this embodiment. That is, V, BC
The dark current of the CD determines the maximum possible exposure time.

After that, further exposure continues (in some cases, at appropriate time intervals, t
= t6 to 1 = 1. The process leading to this will be repeated. Note that in this case, the dark current charge of only V and BCCD cannot be removed, so as a countermeasure, for example, multiple rows of light-shielded pairs of photodiodes 12 and V and BCCD are provided, and some of them are capable of receiving other light. By performing the same operation as the above group, the dark room flow accumulated in the V and B CCDs is held, and the other parts are used for dark current detection, and the output held in the above part is used. If clamp processing is performed externally, dark current compensation for V and BCCD can be achieved.

Finally, the operation after the exposure completion pulse φED is generated at a certain time, t=t9 in FIG. 5, will be described.

As shown in FIG. 5(d), the exposure completion pulse φED generated at t=t9 is given to the timing control circuit 44, and this timing control circuit 44 immediately applies a voltage to the clear gate (CG2) of the dark current detection area 21. VCa is applied as a pulse φCG2, the resulting change in VTG is sampled and held in the same manner as described above, and at t''tlo a transfer pulse φTG is generated to transfer only the signal charge to V and BCOD. During the exposure starting from t=tl, V and B are divided into multiple times and integrated.
The charge on the CCD is synchronized with the subsequent vertical synchronization signals v and D,
It is read from t=to.

In this case, the gate signal φRKCG to the external electrical or magnetic recording medium is 1=1 as shown in FIG. 5(m).
1. From t = t12, it is output at H/7 level. At the same time, V which accumulated dark current charge
, the clamp pulse φcp corresponding to the position of BCCD is also
It is output for each horizontal scanning line and used for final dark current compensation outside the CCD 28.

In the above embodiment, the configuration of the region 21 for detecting dark current provided in the CCD 28 is not limited to that shown in the cross-sectional view of FIG. 6, and may have other configurations.

As explained above, according to the present invention, dark current charges are eliminated inside the image sensor before signal charges are read out from the image sensor, and only signal charges are transmitted from the same photodiode to the same transfer channel. This makes it possible to divide the image into multiple transfers and obtain a still image with a good 8/N ratio even when exposed for an extremely long time.

[Brief explanation of the drawing]

1 is an overall conceptual diagram showing an example of a solid-state image sensor according to the present invention, FIG. 2 is a sectional view taken along II-1 and 1 in FIG. 1, and FIG. 6 is a sectional view taken along III-III in FIG. Fourth
The figure is a connection diagram showing an example of the peripheral circuit of the imaging device according to the present invention, and FIG. 5 is an operation waveform diagram for explaining its operation. 1- Overflow drain (OFI), 2-
Photodiode for light reception, 0FCG), 6-transfer gate, 7- clear gate, 21- dark current detection area, I
-1,8CCD-Horizontal transfer register, V, HCCI)-
Vertical 1a transfer register, 4-embedding channel, 5-electrode. Agent Patent Attorney Sanro Kimura

Claims (5)

[Claims] (1) A light-receiving region that generates and accumulates signal charges according to the intensity of incident light, an unnecessary charge discharge region arranged in parallel on one side of the light-receiving region, and signal charges arranged in parallel on the other side of the light-receiving region. a transfer area, and enables discharge of unnecessary charges from the light receiving area to the unnecessary charge discharging area and transfer of signal charges from the light receiving area to the transfer area at any time. In the imaging device using the element, a transfer means capable of controlling the amount of charge transferred from the light receiving area to the transfer area and a dark current charge detection means are provided on the two-dimensional object imaging element, and the An imaging device characterized in that the transfer means is controlled by a dark current charge detection means. (2) The imaging device according to claim 1, wherein the dark current detection means includes a light-shielded light receiving region, a light-shielded signal charge transfer region, and an overflow drain for dark current detection. Device. (3) Prior to photographic exposure, the charges existing in the light-receiving area and the transfer area are collectively discharged to the outside of the device, and then exposure is started, and after the appropriate exposure time has elapsed, dark current charges are transferred from the transfer area of the dark current detection current. 3. The imaging device according to claim 2, wherein the imaging device is driven to discharge the charge, detect this, and then control the amount of charge transferred from the light receiving area to the transfer area. (4) A patent characterized in that the unnecessary charge discharge region is adjacent to the light receiving region and the signal charge transfer region through gates, respectively, and unnecessary charges can be discharged from both the light receiving region and the signal charge transfer region. An imaging device according to claim 1. (5) When exposure lasts for a long time, the signal charges generated in each light-receiving area are time-divided multiple times and transferred to the same transfer area, and the unnecessary charges generated in the light-receiving area are removed to the unnecessary charge discharge area after each transfer. 2. The imaging device according to claim 1, which is driven to transfer an image to an image.