JPS59102281A - Character/numeral display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alphanumeric display device comprising a random number of elongated elements arranged to form a cross and a diagonal cross within a parallelogram.

The invention furthermore relates to a visual display device comprising a plurality of such alphanumeric display devices.

A typical display device of this kind, in which the parallelogram forms a substantially rectangular shape and is also commonly referred to as a starburst display device, includes one for each arm of each cross. A total of four elongated display elements are used: two elongated display elements, two display elements for each vertical side of the rectangle, and ] display elements for each horizontal side of the rectangle. There is.

When using multiple display elements to form a multiple character (symbol) display device, it is common to multiplex the drives for the display elements to reduce the number of external connections required. In the case of light emitting diode displays, the display elements at the same location of each display device are all connected together so that each display device can be addressed individually. However, such time division multiplexing methods are not widely used in liquid crystal display devices. The ball is like liquid crystal lightning.

There is a limit to the air-light year response, which causes 3 or 4
This is because effectively addressing more than one display device sequentially is prevented. To form a liquid crystal display displaying a large number of symbols, each display device can be configured as a matrix. A display device using the matrix address method is, for example, a magazine.
rOniC3” (May 25, 1978) No. 113~
Mul published by Paul Smith on page 121
jlp teXl, ngLiquiCi-Crys
talDiSplayS'', the contents of which are also included in this specification for discussion.

] Four element display devices are commonly used where a complete alphanumeric display is required, and a 4.times.4 matrix is required to drive such a device. Therefore, a multiple symbol display device requires four terminals for each character symbol and four terminals for a common connecting line for all symbols.

Many display devices having 14 or fewer elements have also been proposed. Such a display device is disclosed, for example, in US Pat. No. 897]
(] No. 12, No. 4184319 and No. 4264
No. 966. However, the display devices described in these patents cannot display complete alphanumeric symbols; instead, they eliminate and reduce the number of elements that do not need to be displayed; The number of is limited. These display devices are used on calendar watches to display abbreviations for past dates.
is suitable for displaying the desired abbreviation, but the number of characters required to display it to indicate the required abbreviation is limited. Therefore, even if the number of connections to each display device is reduced, the display capability of the display device will be sacrificed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device which is suitably constructed and arranged so as to be able to display complete alphanumeric symbols and to require fewer connections than in a four-element display device.

The present invention provides an alphanumeric display device as mentioned in the opening, in which each of the three sides of the parallelogram is formed by a single elongated element, and the parallelogram formed by these single elongated elements is one arm of the cross between two opposite sides is formed by a single elongated element; the remaining sides of the parallelogram are formed by two elongated elements arranged in series;
The cross-shaped arms are formed by two elongated elements arranged in series, and both arms forming the diagonal cross are each formed by two elongated elements arranged in series. do.

The present invention is based on the recognition of the fact that the center and right hand display elements of a starburst display device can be formed from a single element to form a complete alphanumeric display device, and therefore] An advantage is that the number of connections and drive signals required to display a set of symbols is reduced.

One or more single elongated elements can be formed as elongated elements arranged in two elongated rows and connected together so that a single drive signal can actuate both elements simultaneously. In this way, connect the wires for the two vertical elements in the center together and connect the wires for the two vertical elements on the right side.

A standard starburst display device can be easily converted into a display device according to the present invention by electrically connecting it.

The elongated elements may be formed by liquid crystal, and each element is provided with means for selectively supplying an energizing signal. The invention is particularly advantageous for application to liquid crystal display devices for multiple symbol displays. This is because the individual elements in such display devices are usually connected and driven in a matrix configuration.

Therefore, a 4×47) IJ rack, which requires two extra connections, is required for a 4-element display device, but a 4×3 matrix is sufficient for a 2-element display device. While other forms of elements such as light emitting diodes or incandescent lamps are not normally driven in matrix form, the display device according to the invention allows the display device drive information required to be stored to be reduced proportionally to the reduced number of elements. There are also advantages.

The present invention further provides a display device in which the display device is driven in a time division multiplexed manner. It is also an object of the present invention to provide a visual display device for displaying the number of vipers in alphanumeric symbols.

In the display device according to the present invention, each display device is electrically arranged in a matrix of 4 rows and 3 columns, and the 4 row lines of each display device are electrically driven by a common source. simultaneously, so that the three column lines of each display device are supplied with electrical drive signals generated from separate sources.

The invention will be explained with reference to the drawings.

FIG. 1 schematically shows an example of a display device according to the invention, comprising two elongated elements, of which elements ~5 are rectangular. Elements 6 to 8 form a cross, and elements 9 to ]2 form a diagonal cross. The elongated elements ~J2 can be formed in a customary manner, for example as light-emitting diodes, liquid crystal cells or bar-shaped elements of a material having several surfaces of contrasting color. The bar-like members can be optionally positioned to represent a desired character surface.

FIG. 2 shows a letter-numeric symbol that can be displayed by suitably energizing two elements of the display device shown in FIG.

As is clear from Figure 2, each number from 0 to 9,
Possible symbols can be generated in Wg & to represent each alphabetic letter, the only ambiguous of these symbols being the letter S and the number 5. This kind of ambiguous display is the second
This can be done by replacing the symbol shown in the figure as the letter S with the symbol shown in FIG. 3d.

3 shows another symbol from the symbol shown in FIG. 2 that can be generated by the display device of FIG. 1, and FIG. 3a shows a modification of the letter B;
Figures b and 30 show variations for the letter J, and 3e
The figure shows a variant for the letter V, with the 8th f and 3
Figure g shows a modification example for the letter Y, and the ah and 31st
The figure shows a modification to the number 4.

Each elongated element is not limited to being rectangular; these elements can be shaped to provide a more aesthetically pleasing symbol or a more legible symbol.

Furthermore, the display elements 1 to 5 do not necessarily have to form a rectangular shape; for example, the display symbols may be tilted to the right.

Figures 4a and 4b show the voltage values and the connections of these electrodes for a display device formed by a liquid crystal element and configured as an addressing matrix. Figure 4a shows the separate connections for each symbol, and Figure 4b shows the connections common to all display devices arranged in a continuous array r.

For each display device (symbol) in the continuous array, the Jth connection A] is placed to connect to the Jth wire of elements 1, 2, 11 and 3, and the second connection A2 is placed to connect to the Jth wire of elements 4, 5, . The third connection A3 is arranged to connect to the electrodes of elements ]2, 7.6 and 8. There are four connections B], B2. B
3 and B4 as a common line, and in each barefoot device, connect wire B] to the second cage of elements ], ]0 and 8, and connect wire B2 to the second lightning and yuz of elements 9, 6, and 2. Connect B3 to the second electrode of elements 5, 7 and ]J, and connect wire B4 to element 4.
．． Connect to the second terminals of J2 and 3, respectively.

The liquid crystals forming the display elements become transparent or transparent depending on the signals supplied to the first and second ladders of those elements.
It may become opaque. Therefore, the connections A,], A2. A
3. Bl, B2. By selectively applying appropriate signals to B3 and B4, the display device can be activated to display the desired symbol.

In the case of matrix-addressed liquid crystal devices, each display element together with its associated back surface forms the electrical equivalent of a lossy non-peak voltage dependent capacitor. Accordingly, each display device can be represented diagrammatically as row and column conductors interconnected at each intersection by a capacitor, as shown in FIG. The # numbers attached to the capacitors in FIG. 5 are the same as the numbers of the elements they represent. A series of ′? A selection pulse drives each row conductor, and a series of data pulses drives each column conductor.

Figures 6b, 6c, 6d and 6c are rear terminals Bl, B2
．． The waveforms of the selection pulses supplied to B3 and B4 are shown in their entirety. FIG. 6a shows the basic waveform of period T. Each period T is divided into eight sub-periods t1 to t8. Each row ¥4 line follows the basic waveform shown in Figure 6a, and transforms this waveform to generate a positive-going pulse during the first half of period T, and during the second half of period T. In some cases, it is caused to be reversed during the period T by generating a negative-going pulse. Positive-going pulses have a period T
It occurs during 1/8 of the period t□.

12, 13 and t are row conductors Bl, B2 . Corresponding to the period of occurrence of positive going pulses for B, 3 and B4, respectively. Similarly, a negative going pulse also occurs during period h of period T, and period 1. ．． 16.17 and t8 are row conductors B
l, B2. Corresponding to the period of occurrence of negative going pulses for B3 and B4, respectively.

The columns of data pulses that may be applied to column conductors AI, A2 and A3 are shown in FIGS. 6f-6j. Considering the row conductor A], the signal with the waveform shown in FIG.
．． 8 are switched off, the waveform signal of FIG. 6g switches on only the element], the waveform signal of FIG. 6h switches on across the elements, and the waveform signal of FIG. The waveform signal of FIG. 6j switches on only element 3. It is obvious that by combining these waveform signals (FIGS. 6f-63) more than one element can be selected simultaneously.

The amplitude structure of the signals supplied to the row and column conductors is 6a to 6.
A special structure as shown in Figure J can be used. A liquid crystal element is operated by an alternating current signal, and its contrast ratio depends on the effective voltage of the alternating current signal flowing through the element. From the respective waveform diagrams shown in FIG. 6, it can be derived that the effective voltage between the elements that are switched off is ] volts, and the effective voltage between the elements that are switched on is ] 73 volts.

Depending on the requirements of the liquid crystal cell used, voltages in the order of 100 volts can be used.

Figure 7 shows that when n is an integer such as 16,
Block ffJ showing an example of a visual display device for driving symbol display devices 1. ! , +. Such a display device can be used, for example, in a telephone to display a dialed number or a simple message such as "N0MBERENGAGED" (busy).

Input terminal 00 of the device shown in FIG. 7 is supplied with input data in the form of symbols to be displayed. This input data is in the form of a series of AsCl1 codes, which are generated in a clock signal generator [03] and input to a shift register [0] under the control of a clock signal appearing on line [02]. Clock signal generator] It is necessary to synchronize the clock signal generated by the clock signal generator 03 with the input data, or to synchronize the clock signal and the data by some means. When a symbol (data) consisting of
M) The output produced by the decoder which may be of the form [04] is the appropriate one of the lines [06-] to 106-H].
Encoder the line of the book in red] 07: As. This encoder] 07 converts the symbol decoded by the decoder into an element code indicating which element of the display device should be driven to display the symbol. The encoder 107 can also be formed from a ROM, and can be combined with the ROM f14 to generate a display element drive code from an input code.

The output of encoder]07 is on line 108-]~108-
nf to the shift register]09 in parallel (under the clock signal plagiarism I supplied from the clock signal generator]03 via the line]]0). A separate clock signal supplied through the line]]0 causes data to be read from the register]09 to a selected] specific register from the registers]]]-1 to]]]-n. . This specific register is generated by the clock signal generator]03G and is passed through lines 112-1 to 112-n to the register]]]
-1~]]] - Selection is made by the address signal supplied to -H. The outputs of the registers ]]]-] to ]]]-n are supplied to the input terminals of multiple waveform (signal) generators 114-1 to 114-n via lines 113-1 to]]3-n, respectively. Multiple waveform generators 114-1 to 114-n! The clock signal from the clock signal generator 03 is also supplied via lines 5-] to 115-n. Each of these multiplex waveform generators]]4-1 to 114-n generates three separate waveform signals at each of their three output terminals,
These three waveform signals tζ(ll', which are applied to the lines Al, A2 and A3 of each display device, and respectively suppress these waveform signals O) ] 6
− ] = 1 ] 6- Unit displaying n in red]]
Input terminal AI of each display device in 7.

Supplied to A2 and 53.

The clock pulse generator 103 is also connected to Tsukuda's multiple waveform generator]]9 via line ]]8. This multiplexed waveform generator]]9 generates four waveform signals, and these signals are sent to the line B1+ of the display unit 117 via the drive circuit]20.
Combined with B2+B8 and B4. Note that the lines Bl and B2 of each display device in the display unit]]7
, B3 and B4 are connected in series.

In operation, the symbol to be displayed is encoded and supplied to the input terminal 00 and read into the shift register . If these coded symbols are given in parallel form, a parallel input register is used instead of shift register 1()J. When a data word corresponding to a single symbol is read into the shift register [0], the parallel output Ma of the shift register J(1) is transferred to the decoder 104 by the clock signal on the line]C12.
is connected to the input terminal of the decoder, and the A S C
Converting the 'II code into individual symbols, the encoder]07 of the lines 106-1 to 10B-n is made to be addressed. Encoder] 07 is l;',! Each symbol is encoded into a code G, which indicates which of the two display elements should be operated to form the symbol. As a result, the encoder generates a 12-bit binary code, and this binary code is read from the microsignal generator]03 to the register under the control of a clock signal supplied by the line]0. is read into.

The outputs of registers 111-1 to 111-1 under the control of the sum of other clock signals appearing on lines 0
]11-n selected] specific registers 4 (
This specific register is returned/selected by the address signal generated by the clock signal generator No. 03. The address signal generated by the clock signal generator 103 is, for example, a complete A blank signal is also displayed to indicate the end of a word. Therefore, it is necessary for the address signal generator of the display unit to have an instruction signal that indicates when a new symbol or symbol set should be used and displayed. This instruction signal is
For example, when a pushbutton is pressed, the information can be retrieved from the input terminal, or it can be retrieved from the output terminal of the computer. Register 111-1~]]]
It is clear that -n is only addressed if it gives information to be displayed.

The output terminals of the registers 111-]-]]]-n are connected to or connected to the multiplex waveform generators 114-1 to 114-n, respectively;
These multiple waveform generators generate the waveform signals necessary to drive the individual symbol display devices associated with these generators. These waveform signals are generated by a clock signal generator 03 and sent to lines 115-1 to 115-1.
115-n to a multiple waveform generator. The multiple waveform generator is 6th to 6th
Each multiplex waveform generator generates three separate waveform signals, and these signals 16 respectively to the lines AI, A, 2 and A3 of the associated display device.

The other waveform generator 139 is a display unit] 17
Line B of all display devices in ].

B2. Generates waveform signals supplied to B3 and B4. The waveform signals generated by this multiple waveform generator ]] 9 are made dependent on the grI7 to be displayed, these signals using the clock pulses supplied from the clock pulse generator ]] via line ]] 8. is generated. The signal generated by the multiple waveform light detector 19 is supplied to the display unit 7 via a drive circuit 120.

FIG. 8 shows a part of the multiple waveform generators 114-1 to 4-n in a block diagram, and each multiple waveform generator is It has three circuits shown in FIG. As shown in FIG. 8, the first terminal 20]
is connected to the first input terminal of the A/ND-gate 2]1 and the first input terminal of the AND-gate 22]. The output terminal of AND-gate 2] is connected to the control input terminal of analog switch 231, and the output terminal of AND-gate 22 is connected to the control input terminal of analog switch 241.

The ball of the switch 23] is connected to the first input terminal 25 of the single-pole eight-way analog switch 260, and the ball of the switch 24
] is connected to the second input terminal 252 of the switch 260. The ] terminal of the switch 23 is connected to OV, and the second terminal of the switch is connected to the first whistle point of 2■. The [th] terminal of the switch 24 is connected to the potential point 3■, and the second terminal is connected to the potential point [1] of the switch 24. As is clear from FIG. Ball 259 of switch 260 is the output terminal of the multiplex waveform generator, which connects to line A]. Also connect the timing signal (t□ to t81 input terminals to control input terminal 26 of switch 260). , these timing signals actuate the ball 259 of the switch 260, so that the ball 259 of the switch 260 is transferred at an appropriate time to the selection input terminal, that is, to the input terminal 25 during the period tl, and from the time nJ3 to the input terminal 25 during the period t5. The ball 259 is connected to the input terminal 252 during each time period.

Therefore, to generate a signal with the waveform shown in FIG. 6g,
Logic "]" is applied to terminal 20] and logic "o" is applied to terminals 202, 203 and 204. This product method,
AND-gate 2]] generates a logic '°]' at its output terminal during time t1, which connects the ball of switch 23 to OV (till).

Therefore, 0■ is supplied to the input terminal 25 of the switch 260. During the period t□, the ball 25 of the switch 260
9 is connected to the input terminal 25], the room pressure G supplied to the line A1 is 0. During the I period t2 to t, the ball 259 of the switch 260 is connected to the input terminal 25.
3, 255 and 257 in sequence. Input terminal 2
Since the logic level of 02, 203 and 204 is O'', the balls of switches 282, 238 and 234 are all connected to the 2■ side, so there is a voltage of 2V on line A1 during the period t2-t. 1. During the period IHj of the period t5, a voltage of 3V appears on the ball of the switch 241, and this lightning voltage is transferred to the line AI during the period t5, but during the period t6 to t8. During the period t6 to t8, the holes of the switches 242 to 244 are connected to the l··]V side, so a voltage of 2 appears on the line A1 during the period t6 to t8.

Similarly, if the logic "j++" is supplied to the terminal 202, a voltage of 0■ is supplied to the line A] during the period t2, and a voltage of 3■ is supplied to the line A] during the period t6. The signal applied to terminal 203 determines the frost pressure applied to line A during periods t3 and t7, and the signal applied to terminal 204 determines the frost pressure applied to line A during periods t3 and t7.
Determine the voltage supplied to line A during period 8.

To complete B4-1 to B4-114-n, two more circuits as shown in FIG. The other information in the bits generates the outputs on lines A2 and A3. Note that in the illustrated device, the first 4 bits from each register]] are used.

A multiplex waveform generator for generating the drive waveform signals shown in FIGS. 6b-6e] 9 generates a constant waveform signal, ie, a waveform signal that does not change depending on the symbol to be displayed. Therefore -C1 multi-vehicle waveform generator]]9 only receives clock signal input, not data input. Multiple waveform generator]]
9 comprises four similar circuits as shown in FIG. 9, which differ only in the timing signals supplied to them. The first circuit comprises two controllable single changeover switches 30] and 302, the switching of which is controlled by timing signals t□ and t5, respectively. The balls of switches 30] and 302 are connected to the first and second input terminals of another controllable switching switch 303, the ball of which is connected to line B]. The control terminal of the switch SaS is connected to the output terminal of the R3 bistable circuit 304. Such bistable circuit 304 is set by timing pulse t1 and reset by timing pulse t5.

In operation, when a pulse t□ is generated, the switch 30 is set, and the movable point m of the switch connects the hole to the 3V terminal, and at this time, the bistable circuit j... path 304 is also set, so The ball of switch 3 (13 is connected to the ball of switch 801.

Therefore, during the period t□, a voltage of 3V is supplied to the line B1. At the end of the t-work is the ball of switch 801]
It is connected to the potential point of (3), but in this case, switch 1
The state of B remains unchanged, so 1V is supplied to line B until period t5. When the period t5 starts, the ball of the switch 302 is connected to the 0■ side and the bistable circuit 304 is reset, so the ball -□゛1 of the switch 3o3 is connected to the switch 302. Therefore, during the period t5, a direct pressure of 0 is supplied to the line B].

At the end of the period t5, the ball of the switch 302 is connected to the 2■ side, but the state of the switch 303 remains low, so the voltage of 2■ is applied to the line B during the period from t6 to t8. Supplied. Therefore, line B1 has a voltage of 3V during the period to, and during the period t2 to t]
The voltage of ■, or the voltage of OV during the period of t5, t6 to t8
During the period, a voltage of 2■ appears. Similarly, switch 3
11°8]2 and 3]3, a bistable circuit 3]4, and timing pulses t and t6 to generate a multiple waveform signal on line B2; switch 32].

322 and 323, bistable circuit 3]4 and timing pulses t and t7 to generate multiple waveform signals on line B3; switch 83]1332 and 33
3, bistable circuit 334, and timing pulses t 1 and t8 generate multiple waveform signals on line B4.

The clock signal generator (FIG. 7) includes an oscillator and multiple divider and decoder stages to generate the required timing and address waveform signals. The clocking of shift registers ]]], registers ]09 and registers ]]]-1 to 11]-1 to be synchronized with the input data clock, ie, the waveform signal of the multiple waveform generator, is not absolutely necessary. The clock rate for each register can be selected to suit the speed at which the register is engineered to run and the speed at which it supplies symbolic data. It is clear that if the No. 1 data is to be received serially, it is necessary to clock the shift register 0] at the data rate. Similarly, the clock signal generator may be provided with an external input terminal to enable the appropriate counters or registers to be reset when new display information is to be received, and to route the display information to the appropriate display device. It is necessary to do so.

Each of the switches shown in FIGS. 7 and 8 is in the form of a solid-state switch, and these switches can be used to connect a display device, such as a bipolar or MO3 integrated circuit with small, medium or large scale integration. Depending on the technique used to form it, it can be of various forms.
& switching circuits are well known to those skilled in the art.

The display device having the configuration shown in FIGS. 1 to 4 allows alphanumeric symbols to be completely displayed, and requires a larger display device than the conventional four-element display device or the 5×7 dot matrix display device. The number of connections can be reduced. In particular, the number of interpretations for a 6-character display can be reduced from 68 to 52. Furthermore, the display information required to be stored can be reduced by about 4%.

Therefore, if the display device is formed into an LSlSl type together with the display unit, the number of bins during mounting can be reduced, the chip area can be greatly saved, and the cost of the entire display device can be reduced.

In addition, although a liquid crystal type display device has been described in the embodiment, any type of display element (tlJ) can be used as the display device. However, in this case, the driving method should be The circuit will need to be redesigned, but the benefits are still that mt is reduced and less display information needs to be stored.A standard] four-segment display device It can be used with the drive circuit described above by connecting two elements together, corresponding to elements 2 and 6.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of a display device according to the present invention; FIG. 2 is an explanatory diagram showing an example of alphanumeric symbols that can be generated with a display device according to the present invention; FIG. 3 is a display also according to the present invention. Explanatory diagram showing other examples of alphanumeric symbols that can be generated by the device; 4a and 4b
The figure is an explanatory diagram showing the electrodes of the display device according to the present invention and the connections between these electrodes when formed as a liquid crystal display device; FIG. 5 shows the electrical connections of the display device shown in FIG. 4 as a 4×3 matrix. FIG. 6 is a waveform diagram of a typical driving signal for the display device of FIG. 4; FIG. 7 is a block diagram showing an example of the visual display device according to the present invention; FIG. FIG. 9 is a logic circuit diagram showing an example of a j-th type multiple waveform generator used in the device shown in FIG. 7; FIG. 9 is a logic circuit diagram showing an example of a second type multiple waveform generator used in the device shown in FIG. be. 1~]2...Display element 100...Data input terminal]0]...Shift register ]03...Clock pulse generation 8]04...Lever) i-107...
Encoder 109...Shift register]"1...
Register]]4.119...Multiple waveform generator 116, 120...Drive circuit ]]7...Display unit 2]]~2]4.22]~224...AND-
Gate 23] ~234.24+1~244...Analog switch 260...Single pole 8 trace analog switch 3
0]~803.811~3]3.321~328.33
1 to 333... Single changeover switch, 304.814.324.334... R3 bistable circuit. Patent 1jM person N.B.Philips FluirampenfabrikenF.I Ft'g, 2゜(al (bl fc) (dl[
e) (f) (g) fhl (
il〜・5 A1 A2 A3

Claims (1)

[Scope of Claims] L An alphanumeric display device comprising w several elongated elements arranged to form a cross and a diagonal cross within a parallelogram, each of the three sides of the parallelogram being a parallelogram formed by a single elongated element, one arm of a cross between two opposite sides of the parallelogram formed by these single elongated elements; The remaining sides of the ML cross are formed by two slender elements arranged in series, and the other arm of the ML cross is formed by two slender elements arranged in series in the front. An alphanumeric display device characterized in that each arm is formed by two elongated elements arranged in series. Ward In the display device according to claim 1, 1
The plurality of mono-elongated resistors are formed by two elongated elements arranged in series, and these elements are connected together so that both elements are actuated simultaneously by a single drive signal. An alphanumeric display device characterized by: & An alphanumeric display device according to claim 1 or 2, characterized in that the elongated elements are made of liquid crystal and are provided with means for selectively supplying electric signals to each element. A visual display device for displaying several alphanumeric symbols, comprising a plurality of display devices according to any one of claims 1 to 3, wherein the display devices are driven in a time division multiplexed manner. A display device characterized in that: (v) In the display device according to claim 4, each display device is electrically arranged in a matrix of 4 rows and 3 columns.
f#L, the four row lines of each display device are simultaneously supplied with electrical drive signals from a common source, and the three column lines of each display device are supplied with electrical, drive signals generated from separate sources. A display device characterized in that: