JPS5899267A - DC-DC converter - Google Patents

Abstract

PURPOSE:To stabilize DC output of constant voltage and current to be supplied to the load, by a method wherein switching pulse width or period in a switching pulse generator is controlled by detecting output obtained from a detecting resistor of detecting means. CONSTITUTION:A current mirror circuit MV constitutes voltage detecting means DV, and primary side between input end A and common end C of the current mirror MV is connected between DC output ends 16a, 16b. The input end A of MV is connected through an input resistor 21 to the DC output end 16a, and the common end C of MV is connected to the DC output end 16b through primary side between input end A and common end C of a current mirror circuit MI to constitute current detecting means DI. Output end B of the current mirror MV is grounded through a detecting resistor 22, and further output end B of the current mirror MI is grounded through the detecting resistor 22. In this constitution, DC output to be supplied to the load can be made constant voltage and current quite stably.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a transformer having a primary winding and a secondary winding, and the primary winding #! is connected to the DC input terminal through a switching element, the secondary winding of the transformer is connected to the input terminal of the rectifier circuit, and the output terminal of the rectifier circuit is connected to the input terminal of the rectifier circuit. W on the outflowing blade edge! The present invention relates to a modification of a DO-DC converter in which the switching element is controlled by a switching pulse from a switching pulse generating circuit.

The @DO-DC converter detects the DC output supplied to the load connected to its DC output terminal, and uses the detection output to control the switching pulse gutter tip circuit to generate the switching pulse expected from this. If the width or period is controlled, the DC output supplied to the load can be made into a constant voltage, a constant current, or a constant voltage and current.

In order to be able to control the switching pulse generation circuit in this way,
When detecting the DC output supplied to the load, the detection means must be configured in a manner that does not affect the DC output supplied to the load. In order to detect the DC output supplied to the load, it has been proposed that the detection means be constructed using a transformer or a photocoupler. has been done.

However, if such a detection means is constructed using a transformer or a photocoupler, it is difficult to integrate the transformer or photocoupler into a semiconductor integrated circuit, so the detection means as a whole cannot be integrated into a semiconductor integrated circuit. ,-therefore D
The O-DO converter as a whole had drawbacks such as a small size and a certain degree of shortcomings in reducing the cost.

Therefore, the present invention aims to propose a novel controlled DO-DO converter that can make the DC output supplied to the load constant voltage, constant eL current, or constant voltage current without the above-mentioned drawbacks. , will become clear from the detailed explanation below.

No. 111 shows an example of a DO-DO converter according to the present invention, which has a transformer 3 having a primary winding 1 and a secondary winding 2, and both ends 4a and 4b of the primary winding 1 of the transformer 3.
A pair of DC input terminals 8a and 7, through which the input DC current II7 is oscillated through the collector gate of, for example, a transistor 6 as a switching element 5, which is controlled by a switching pulse 8P obtained from a switching pulse generation @%S5, which will be described later. 8bE is connected, therefore the DC input terminal 8a
And the input DC power $7 is connected to the 8b cabinet, and the switching resistor 5 is connected to the switching path described later at the ste 8P.
w, the secondary winding 1lli2 of transformer 3 -
jlli19m and? It is designed so that a pulse output can be obtained during the battle.

Also, both ends 9a of the secondary winding @2 of the transformer 5 and ? b is I!
: connected to the pair of input ends 12m and 12b of the current circuit 11, while the pair of output ends 13m and 15 of the rectifier circuit 11
One output end 13m during 1s is directly connected to one output side 416m of the pair of DC output ends 16m and 16b to which the load 15 is connected, and the other output end 13b is the input of a p-rent mirror circuit MI to be described later. It is connected to the other DC output end 14b via the primary side between the end arm and the common end C. In this case, an example of the straight aim path 11 is that the anode is connected between the input end 12m and the output end 1Aa, and the input end 12 is set as II!
The rectifier diode 17 that can be connected, and the output terminal 16 and 13
It has a smoothing capacitor 18 connected to the input terminal 12b and the output terminal 15b. Therefore, between the output end 13m of the #i-path 11 and Thb, both M? The pulse outputs obtained at the terminals m and 9b are blue, and the output terminal 13a is set to have a positive polarity (DC output voltage 1). Also, the load 15 is applied to the DC output end 16m and 16b.
The primary side between the input terminal M and the common terminal 0 of the mirror circuit MY is connected to the resistor 21, which will be described later, and the primary side of the input terminal M and the common terminal 0 of the current mirror circuit MI, which will be described later. If the load 15 is connected through the output end 13a side, the output fi16m, the negative #15, the output end 14b, and the current mirror path M to be described later.
The direct current output tfi I, which passes through the input end of I and the common end C between the input end of the current mirror circuit MY and the common end C is made to flow. 111LR1 that passes through the resistor 21 described later on the primary side
2 is made to flow, so that the secondary winding of transformer 3 [
Arriving at the pulse output obtained at 2 p@trend 9a and 9,
From the output terminal 13a side, the DC output terminal R1 and the sum of DC output terminals R1 and 12 * (11+12) flow out directly from the DC output terminal 16a, and the output terminal 1sbluci[g output current (1,
+I,) is made into a loincloth from the DC output end 16b.

Furthermore, a load 1 connected between the DC output ends 16m and 16b
5&c A current mirror path MY for configuring a voltage detection means (generally referred to as DV) for detecting the DC output voltage supplied, that is, the DC output voltage between the DC output ends 16m and 16b (2), and the DC output end. It has a current mirror circuit MI for configuring current detection means (generally referred to as I) for detecting the DC output end ff1l supplied to the load 15 connected to the 16m and 16b cabinets. In this case, each of the current mirrors WAjl)MY and MI are
As usual, it has an input end A, an output end B, and a common end 0 which is common to the input end A and the blade end B, and between the input end M and the common end C. We assume a configuration in which the primary side is the output terminal B and the common terminal 0, and the output terminal B and the common terminal 0 are the secondary side.
A transistor Q1 of the NPN type controlled by the current passing through IO connects its collector to the input terminal A1 with a common terminal +
11110, and the output @
B and the common terminal 0, the NPN II transistor Q is driven by the current through the input voltage and the common terminal C.
2 is connected in such a manner that its collector is connected to the output terminal B and the construction terminal is connected to the common terminal C, and the transistors Q1 and Q
It has a configuration in which two paces are connected to the input end Atcm.

Thus, the primary component of the input terminal A and the common terminal C of the current mirror circuit MY constituting the voltage detection means DV connects the input terminal M to the input resistor 2 between the DC outputs j1116* and 16b.
1 to the DC output 14m, and the common end 0 to the input X of the current mirror I path MI to constitute the current detection means DI.
It is connected to the DC output end 16b through the primary side between A and the common end C. Further, the output end B of the current mirror circuit MY is suffixed so as to be connected to the grounded end of a DC converter 26, which will be described later, through a detection resistor 22.

In addition, the primary side between the input end A and the common group C of the current mirror path MI for forming the current detection hand [DI\rII] is connected to one output end fib of the rectifier circuit w611 described above and the DC output; 416b described above. At the same time, the input terminal is connected to the DC output terminal 16b.
The manner in which the common terminal 0 is connected to the output 1113bGcm is shown below.
connected. Further, the output end B of the current error circuit MI is grounded to be connected to the grounded end of the DC 1i 126, which will be described later, through the detection resistor 22 described above.

Furthermore, the DC output end tjm is the output end 1 of the *, it circuit 11.
DC output voltage V obtained at 5m and 15b14, or DC output voltage obtained between DC output ends 16& and 16b■
Through the transistor circuit 25 controlled by
One end is connected to the other end of a DC current 1124 which is grounded.

In this case, an example of the transistor 1125 is an NPN II transistor 29 at the rectifier output terminals 13m and 15b.
and the transistor sO of PNP II in series connect the collector of the transistor 29 to the output end 15m, the emitter to the transistor 30 node, and the base of the transistor 3o to the connection midpoint 5 of the resistors 27 and 28.
Connected to 1. Thus, the DC output terminal 16& is the collector and emitter of the transistor 29, and the transistor 29
and 50 through the connection midpoint 32 of the DC power supply 26
Connected to the ungrounded end. In this case, the direct R% umbrella 26 has a polarity with the ground side being positive. Also, the connection midpoint 61 of the resistors 27 and 28 is the bypass capacitor 53.
It is grounded through.

Also, both ports 4 & 4b of the primary winding 1 of the transformer 3 mentioned above
It has a switching pulse generation circuit 55 that generates a switching pulse 8P for controlling the switching element 5 connected to the DC input terminals 8a and 8b. In this case, the switching pulse generation circuit 35
and a pulse generator 57 whose output is controlled. The comparison circuit 56 has two input terminals s8a and 5@b,
It has an omniscient configuration with one output IIs 58e, and the input end 38m is connected to the above-mentioned detection resistor 22.
The input end 58b is connected to the other end of the reference DC power supply 59 whose end is grounded, and therefore the detected output voltage v1 obtained from the output end 58e across the detection resistor 22 is It outputs a comparison output 8 having a voltage difference (V, -V4) from the reference voltage 4 of the reference IIL#1 power supply s9. Also pulse generation Mk57
has a configuration known per se for generating pulses whose period is modulated depending on the input of a control voltage, and therefore by receiving the comparison output 2 from the comparison path 36 as a control voltage: A switching pulse is generated whose width or period is modulated according to the voltage (Vs-V4) of the comparison output l. Therefore, the switching pulse is generated @WIrS5. vl
Then, the width or period of the switching pulse 8P obtained from the switching pulse generation circuit S5 is expressed as l1.
11I, it is designed to be controlled. Therefore, this switching pulse generation tlj155
The switching pulse SP obtained is supplied to the base of the transistor 6 of the switching element 5 mentioned above,
Therefore, the transistor 6 is turned on and off by the switching pulse 8P.

The above is an example of the configuration of the DO-DO converter according to the present invention. According to this configuration, the DC input terminal 81 and the
M - Connect DC power supply 7 and generate switching pulses -
The switching pulse 8 is activated by activating the path s5.
Get P.

By the switching operation of the switching element 5, a pulse output is obtained at both ends of the secondary winding ml of the transformer 5, and therefore, as described below (output terminals 15m and 15kMM of the rectifier circuit 11 - DC output voltage V, In addition, if the load 15 is connected to the DC output terminals 161 and 16'b in advance, the first order of the input terminal of MI and the common terminal 0 can be obtained as shown below. A DC output current 1. flows through the side, and a DC output voltage v2 is returned across the fundamental load 15 and thus between the DC output terminals 14aJL and 16k.

Furthermore, a current I2 flows through the resistor 21 at the input terminal of the current mirror circuit MY and the primary side of the common terminal 0.

Also, now the transistors 29 and 50 of the transistor circuit 25
are on and off, respectively, then m falls on the primary side of the current mirror circuit MY! , is flowing from the DC power supply 26 to the resistor 22, the output 1llIB of the current mirror circuit MY, the secondary side of the common terminal 0, the output end tab and the input end 12b of the rectifier path 11, and the system voltage. The secondary 4[2 and % diode 17 of the rectifier circuit 11,
Transistor 2 of transistor circuit 25! The DC current #L passing through those I[ is detected by the DC power source 26 due to the current flowing through the primary side of the circuit MI. The output terminal B of the current mirror circuit MI and the secondary side of the common terminal 0 and the I
[1m1g1llll output end 15b and input end 12b
, transformer black secondary 41) JII2, and aR circuit 11
The direct a current 4 flows through the diode r17 and the transistor 29 of the transistor circuit 25 through these *#c.

Transistor j12 of life transistor route 25? and 5
0 are off and on, respectively, because the I-order tsct*I2 of the current mirror circuit MV is flowing, the DC power supply 26 connects the detection resistor 22 and the secondary of the current mirror path MY. side and the transistor 50 of the transistor path 25 through their application.
I.

falls, and since current I is flowing through 1*Il of current mirror 1iml1MI, direct #1llllIlu
Therefore, the detection mm resistor 22 and the current mirror circuit MI 2
The next side and the transistor in the transistor path 2s! Direct ml electric 1 that fulfills those wishes with 50! I4 is the one that flows.

At this point, a resistor 27 and q2 of 11k is connected to the transistor path 25.
The potential of the connecting midpoint 51 of $ (this is V) is, if the resistance values of 27 and 28 are equal, the potential of the straight mai blade ends 14m and 16- is V and 5, respectively. In other words, it is given by . Therefore, the base-emitter voltages of transistors 29 and 50 are now equal to the voltage vm
m, and when the voltage of direct 5 tab is vs, ■, ≧V! i+V,, --------(If the following relationship exists, only the transistor 29 is turned on among the transistors 29 and 5G, and V, ≦vi −vlm・
--- If the relationship (3) is satisfied, the transistor 5
Only 0 turns on.

Further, when the transistor 29 and sO of the transistor circuit 25 are on and off, respectively, the detection resistor z zsc
IC style 1. and ■4 flows, so the voltage V obtained across the detection resistor m22 is the resistance value of the detection resistor 22.
22, V, m 14. CI, + 14) and the transistor -2? of the transistor circuit 25. When and sO are off and on, respectively, the voltage V3 obtained from both ends of the detection m resistor 22 is
V, -s R,, CI, + 14), but for the sake of simplicity! , and engineering are generally Il, and ■4 and X4 are generally Ib.

Vs −R2ff1”a +lb) =・---(4
). The voltage Vj expressed by this equation (4) is supplied to the comparison circuit 56 of the switching pulse generation circuit 55.

Then, this voltage vJ is compared with the voltage v4 of the reference direct Kl source S9, and the pulse generator 57 is controlled by the comparison output 11 to be controlled according to the number or period of the switching layer pulse 8P. It is something that On the other hand, if the duration or period of the switching pulse 8F is controlled, the adjustment a
The DC output voltage V obtained at the output terminals 15m and 15b of m1111 increases, and as a result, the currents ff1I and I flowing through the detection resistor 22jC change, and the voltage V becomes the difference between the voltages vs and v4 ( V, -V4) and changes in the direction of zero. Therefore, if a sufficiently high resistance of 1 is applied as the ratio II &- path 56, then the 11th current I, l will change the resistance value of the input resistor 21 connected in series with the primary side of the current mirror circuit MY to - Also, the force Vnt of the current mirror circuit MY (the error ratio is N1,
ml! Now for simplicity am-road 1' 111D m force 1i
15aJj and 15b5iL Obtained voltage V, and output terminal 1
4m and 14b1MIM - resulting voltage V! The voltage V that is equal to . If so.

1, (V, /Rg)N,---(6).

Input current RI is given by Nb, which is the input current ratio of current mirror circuit MI.

I, ■I, N, ---<'I) It is expressed exclusively in

Therefore, from equations (6) and (7), 111 (6) The following relationship is obtained.

[*clll! Ia and Ib (I, and I4, or I5
and I4) as described above, as force blade edge 14 a 1kU 14 b ノILY, Ahi V4
tll rises L, thus connecting transistor path 25 4
51 IE rank V, increases. For this reason, the potential V
.

The equation (2) is satisfied, and the transistor 2t of the transistor circuit 25 is turned on. Therefore, in general, if mfEv has the relationship of the above-mentioned equation (3), then the transistor 2 of the transistor circuit 25? is on and has the relationship of the inlet) equation) the tensor 50 is on, and therefore the voltage V is the value (V, +V□) on the right side of equation (2) mentioned above and the value on the right side of the working force ( V, −V□), but in steady state the % voltage V, is the voltage V.

By doing so, the following relationship can be obtained: Vp-VB + V□ --- (11).

Therefore, in steady state #C, you can improve by 1! I, is I,,
Ib is I4.

In addition, since the bypass condenser 5s is connected to the connection middle point 51 of the transistor circuit 25, the output terminals 16m and 1
Even if the 6b IC AC component is superimposed, it is bypassed through this capacitor 55, so the base and emitter voltages of the transistors 29 and 50 are not affected by the AC component, and therefore the transistors 29 and 50 act as constant current sources. Therefore, it is possible to obtain that IIEfiI and Ib mentioned above are not affected by the interaction.

As described above, according to the DO-DO converter according to the present invention described above, the detector i! using the current mirror circuits MV and Ml, the detection resistor 22, and the transistor circuit 2S!
Direct R supplied to load 15#c using IDV and DI
The output is detected using the voltage V obtained from the detection resistor 22#, and the detected output drives the switching pulse generation circuit ss to the switching layer bar a=
It is possible to control the DC power (voltage v2 and current I, ) supplied to the load 15 to a constant voltage current by controlling it to be controlled with x8PID@ or a period.

The detection means DV and DI used in this case are designed to detect the DC output supplied to the load 15 through the paths of the currents 11 and I, which will be described later, so the detectors 1tLDv and Therefore, it does not affect the direct IL output c14 supplied to the load 15#c. In addition, the detection means DV and DI are connected to each other.
V and MI, the resistor #t22 and the transistor path 2s are used to detect the detecting means DV and DI.
can be made into a semiconductor integrated circuit.

Therefore, according to the present invention, the DC output supplied to the load is reduced to 1
A low-cost 0-DO device that can stably generate constant voltage and current.
It has a large mold that can provide Conver I.

Note that in #c1 above, we have described the DO-DO converter I that can convert the DC output supplied to the load into a constant voltage current, but in detail IIall! Akira omits this, but is glad 2
As shown in the figure, in the configuration described above in Figure 81, the current color circuit MI is omitted.
The same structure as in the case of 1I can be used to make the DC output supplied to the load constant voltage, and as shown in FIG. The configuration is the same as that shown in Fig. 1, except that the 1st path MY and the resistor 21 are omitted, and the DC output supplied to the load is made to be a constant current. If the configuration is such that the DC output supplied to the load can be made constant as shown in FIG. 2, the load l is the same as the first term on the right side of equation (8).

DC output voltage V. is obtained.

In addition, if the configuration is such that the DC output supplied to the load number can be made constant w1rlL as shown in Sa#, the load will have a voltage of 1-V ---
DC output t611.al bR2Z . is obtained.

Furthermore, the above description merely shows a few embodiments of the present invention, and various changes may be made without departing from the spirit of the present invention.

4 M-'s wrathful l! Beak Ill shows an example of Do-Doyxn A-1 according to this arc Connection g%$91211 and Joy51141 respectively book v
FIG. 3 is a connection diagram showing another example of the hvsc DO-DO bumper.

In the figure, 1- is the primary 11m, 2 is the secondary winding, S is the transformer, tI is the switching element, 1lal and 811 are the DC input terminals, 11 is the IIIL- path, 12 is the input terminal, and 131 is the DC input terminal. and 1511 is the output end.

55 is a switching pulse generation path, No. 15 is a load, 1
6m and 14 have a straight blade end, M is an input end, B is an output end, %0 is a common end, M ma and MI4 pint construction two circuits, 2241 afijltK, 2 S is a transistor path, 26 is a straight end. #! Indicates each power supply Applicant: Nippon Denkoden-Public Corporation

Claims (2)

[Claims] 1. A transformer having a primary winding and a secondary winding, both ends of the primary winding of the transformer are connected to a pair of DC input ends through a switching element, and both ends of the secondary winding of the transformer are connected to a pair of DC input ends through a switching element. are connected to the input ends of the mm path pairs, and the wrinkle rectifier all
a pair of output ends are connected to the first and second DC output ends,
In a Do-Do converter in which the switching element is controlled by a switching pulse from a switching pulse generator, the DC current is supplied to a load connected between the first and second DC output terminals. a current mirror 7 circuit having an input end, an output end, and a common end to the input end and the output end; The primary side between the input end and the common end of the @ path is connected between the first and second DC output ends, the output end of the current mirror circuit is connected to one end of the DC power supply through a detection resistor, and the The first or second DC output end is connected to the other end of the DC power supply through a transistor circuit controlled by the voltage of the [m output W! The switching pulse generation circuit is controlled by the detection output obtained from the detection resistor to control the frequency or period of the switching pulse obtained from the switching pulse generation circuit. A DC-Do converter that makes things worse. 2. It has a transformer having a primary winding III and a secondary winding,
The W# end of the primary winding of the wrinkle transformer is connected to a pair of DC input ends through a switching element, and one end of the secondary winding of the transformer is connected to a pair of input ends of the Wataki circuit.
The output terminals of the pair of iL circuits are connected to the first and second DC output terminals.
In a DO-Do converter in which the switching element is controlled by a switching pulse from a switching pulse generation circuit, the load is connected between the first and second DC output terminals. a detection means for detecting a direct current output supplied to the current structure, the detection means having a current mirror circuit having an input end, an output end, and a common end to the human power end and the output end; - The primary side between the input terminal and the common terminal of the circuit is connected to either one of the pair of output terminals of the above-mentioned integer #1 circuit and this
The output terminal of the circuit is connected to one end of the DC power supply through a detection resistor, and the output terminal of the circuit is connected to one end of the DC power supply through a detection resistor. 1
The DC output terminal of the DC output terminal is connected to the other terminal of the DC power supply through a transistor circuit controlled by the voltage of the DC output, and the switching pulse generation circuit receives a signal from the detection output obtained from the detection resistor. to control the width or period of the switching pulse,
A DC-Do converter that is controlled in a controlled manner.