JPS5882552A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5882552A JPS5882552A JP18159681A JP18159681A JPS5882552A JP S5882552 A JPS5882552 A JP S5882552A JP 18159681 A JP18159681 A JP 18159681A JP 18159681 A JP18159681 A JP 18159681A JP S5882552 A JPS5882552 A JP S5882552A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- projection
- base material
- casing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は低融点ガラスの溶融により絶縁体Jli&にリ
ードフレームを取付けてなる構造を有する半導体装置に
係p、*に絶縁体基板にリードフレームt−城付ける際
にリード7V−ムの各リード先端上向を同一平面上に揃
えることができる構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a structure in which a lead frame is attached to an insulator by melting low-melting glass. This invention relates to a structure in which the upper ends of each lead of a 7V-me can be aligned on the same plane.
半導体集積回路(工0)素子を気密封止してなる半導体
装置の一つとして、セラミック等の杷縁体基II(以下
素子状118器基体と称する)に、低融点ガラスにより
、リード7V−ムを固着してなる半導体装置が適用され
ているO
第1#A乃至g4図はかかる半導体装置の組み立て工@
0概略を示す。As one of the semiconductor devices formed by hermetically sealing a semiconductor integrated circuit (process 0) element, a lead 7V- Figures 1 #A to g4 show the assembly process of such a semiconductor device.
0 outline is shown.
かかる技fiKあっては、セラミック材から構成される
素子収容1!器基体lは、第1図に示される如く、その
一方の主面の中央部に凹状素子収容部8が配設され、他
は一様な厚さとされる。With such a technique fiK, the element housing 1 made of ceramic material! As shown in FIG. 1, the device base 1 has a concave element accommodating portion 8 disposed in the center of one main surface, and the other parts have a uniform thickness.
そして、lI記累子収薯容暢基体1olll記主面上に
は纂2図に示される如く、低融点ガラス層3が配設され
、轟該低融点ガラス層3が溶融状態とされて例えばコバ
ール等からなるリードフレーム番が固jllされろ。か
かるリードフレーム番は後に切断分離され外部接続端子
を構成する。As shown in Figure 2, a low melting point glass layer 3 is disposed on the main surface of the fluent substrate 1, and the low melting point glass layer 3 is brought into a molten state, for example. The lead frame number made of Kovar etc. should be fixed. This lead frame number is later cut and separated to form external connection terminals.
次いでIII紀素子収容部2に半導体集積回路素子が収
容固着され1m該半導体集積回路素子の電極と前記り−
ドフV−五番のリード内端部4′とがフルンニワム線等
によam絖(ワイヤボンディング)される@(かかる状
態は図示せず)
−万、前記素子収容容器基体1に対応する大きさt−有
し且つ一方の工面に前記素子収容部2に対応する領域を
除いて低融点ガラス層が配設されたセラミック材からな
る蓋部材が準備される。かかる蓋部材は第3図に示され
るように前記素子収容部を蝋って配置され、前記低融点
ガラス層の溶融。Next, a semiconductor integrated circuit element is housed and fixed in the III-stage element housing part 2, and the electrodes of the semiconductor integrated circuit element and the above-mentioned electrodes are connected for 1 m.
Dofu V-The inner end 4' of the fifth lead is wire bonded with a full wire or the like (such state is not shown) - 10,000, with a size corresponding to the element housing container base 1. A lid member made of a ceramic material is prepared, which has a T-shape and has a low melting point glass layer disposed on one side except for a region corresponding to the element housing portion 2. As shown in FIG. 3, such a lid member is disposed over the element accommodating portion, and the low melting point glass layer is melted.
固化によって素子収容容器基体lに固着される。It is fixed to the element housing container base l by solidification.
第3図において5はft部材を示す。In FIG. 3, 5 indicates the ft member.
しかる恢、前、記リードフレーム4は、第3図のA−A
’に沿って切断され、半導体装置が完成される0
しかしながら、このような半導体装置にあっては、前記
第2図に示されるリード7V−ムのIJ−ド内端部4′
各々の上面を同一平面に揃えることが困崩であり、@記
ワイヤボンデイング工程でボンディング不良等の不都合
を生じてしまう。However, the lead frame 4 shown in FIG.
However, in such a semiconductor device, the inner end 4' of the lead 7V shown in FIG.
It is difficult to align the upper surfaces of each to the same plane, which causes problems such as poor bonding in the wire bonding process described in @.
かかるリードフレームのリード内端部l各々の上面の同
一平面化は、当該リードフレームのプレス加工時にリー
ド内4 @ 4’各々の上rTiを一様な平面とするこ
とが1峻である点並びに前記票子収谷谷器基、Ill上
に配置される低融点ガラス層3は第2図又は第4図(I
E3FIAB−B’断面)に示されるように厚く、溶融
した轟該低融点ガラス層s上に浮いた吹聴で置かれ轟該
低融点ガラス鳩3の固化とともK11着される前記リー
ドフレーム4のリード内端s4′各々を同一平面に揃え
ることが1崩である点等からして、龜めて1崩でありた
。The top surface of each lead inner end l of such a lead frame is made to be on the same plane because it is important to make the upper rTi of each lead 4 @ 4' a uniform plane during press processing of the lead frame, and The low melting point glass layer 3 disposed on the above-mentioned holder is shown in FIG. 2 or 4 (I
As shown in E3FIAB-B' cross section), the lead frame 4 is placed in a floating manner on top of the thick, molten low melting point glass layer s, and is attached to K11 as the low melting point glass layer 3 solidifies. In view of the fact that aligning the inner ends of the leads s4' on the same plane is a perfect solution, it was a perfect solution.
不発v!AFiこのような従来の半導体装置の有する欠
点を除去し、素子収容容器内におけるリード内端部+′
t fill−平向上に配置可能として、ワイヤボンデ
ィングエ1stすみやかに高い慣頼注をもって実施する
ことができるリードフレーム固着構造を提供しようとす
るものである。Misfire v! AFi eliminates the drawbacks of conventional semiconductor devices,
It is an object of the present invention to provide a lead frame fixing structure that can be placed on the flat surface and that allows wire bonding to be carried out quickly and with a high degree of customary effort.
この九め、不発明によれば、l/A子収谷谷器基体の一
方の工面上に、#L4体素子が搭載され、且つ前記工面
上にlImの外部il!続端子がガラスにより固着され
、前記半導体素子の電価と前記外#接続端子とが導゛颯
的に儀絖されてなる半導体装直において、前記外部*a
端子には前記半導体軍子の固N部近傍において前記素子
収答容(転)基体に接する如き凸状部が配設されてなる
ことを特徴とする半導体装置が提供される。According to this ninth non-invention, the #L4 body element is mounted on one of the surfaces of the l/A element base, and the external il of lIm is mounted on the surface. In a semiconductor device in which a connection terminal is fixed with glass and the voltage of the semiconductor element and the external connection terminal are arranged in a highly conductive manner, the external *a
There is provided a semiconductor device characterized in that the terminal is provided with a convex portion that contacts the element housing (transfer) base in the vicinity of the solid N portion of the semiconductor element.
以下本発明による牛導体W装置を実施例をもってi#P
細に説明する。The following is an example of the cow conductor W device according to the present invention.
Explain in detail.
第6図は本発明による外部接続端子の凸状部の実適例を
示す。同図は複数ある外部接続端子のうち一本だけを示
したものである。同図(a)−に)はリード内端部に至
る中間に凸状部をプレス加工により折曲げて成形し九も
の、(e)および(f)はリード内端部t−同様に折曲
げて成形したものであシ、(g)はポンチによる張出し
刀ロエにより突起を成形し良書、(h)はリード内y!
a部と甲関部の2−所に凸状部を成形し良書、(1)は
部分的に厚くして凸状部を成形した例を示す。なお凸状
部の成形はリードフレームを成形加工する工程で同時に
成形を行なうことが作業性およびコストの面から望まし
い。FIG. 6 shows a practical example of the convex portion of the external connection terminal according to the present invention. The figure shows only one of the plurality of external connection terminals. In the same figure (a)-), the convex part is bent and formed by press working in the middle leading to the inner end of the lead, and in (e) and (f), the inner end of the lead is bent in the same way. (g) is a good book with the protrusions formed using a punch and a protrusion, (h) is inside the lead!
(1) shows an example in which convex portions are formed in two places, the a part and the instep part. (1) shows an example in which the convex parts are partially made thicker. Note that it is desirable from the viewpoint of workability and cost that the convex portion be formed at the same time as the process of forming the lead frame.
第6図乃至第9図は本発明による半導体装置の組み立て
工程の概略を示す。6 to 9 schematically show the assembly process of a semiconductor device according to the present invention.
本発明によれば、アルミナ(AttOs)等のセラミッ
ク材から構成される素子収容容器基体工01は1ga図
に示される如く、その−万の工面の中央部に凹状素子収
容部1(lが配設され、前記素子収容容器基体101の
前記工面上には、素子収容5102を除いて融点300
℃乃至650℃の。According to the present invention, an element housing container base structure 01 made of a ceramic material such as alumina (AttOs) has a concave element housing portion 1 (l) disposed in the center of its -10,000-dimensional surface, as shown in Fig. 1ga. The melting point is 300 on the surface of the element housing container base 101 except for the element housing 5102.
℃ to 650℃.
酸化鉛(Fl)O)−酸化礪軍(Bt On )系ある
いは酸基体101上の低融点ガラス層の厚さは、リード
フレームのll1L夛付は後かかるリードフレームの凸
状Wht含んだ犀さとほは同一の厚さとなる。すなわち
同−半一管形成し得るガラス量を有する厚さとされる0
かかる状+atg6図に示す0同図において103は低
一点ガラス層を示す0
久いで、素子収容容器基体101の前記低融点ガラス層
103上に、コバール、42合金等の銑ニッケルコバル
ト合金あるいは銑ニッケル合金からな9.第6図に示す
如く低融点ガラス層103との固着部に凸状all ’
J 5t−形成し九リードフレームを載賦し九盪、低融
点ガラス層103の溶融1直まで加熱し、しかる後冷却
してリード7レームを素子収容容器基体101に固着す
る。The thickness of the low melting point glass layer on the lead oxide (Fl)O) - lead oxide (BtOn) system or the acid substrate 101 is determined by the thickness of the lead frame containing convex wht after the lead frame is attached. The thickness will be the same. In other words, the thickness is set to have the amount of glass that can be formed into a half-tube.
In this figure, 103 indicates a low-melting point glass layer 103. After a while, a pig-nickel-cobalt alloy such as Kovar, 42 alloy, or a pig-nickel alloy is applied on the low-melting-point glass layer 103 of the element housing container base 101. Made of alloy9. As shown in FIG.
J 5T is formed, nine lead frames are placed thereon, and heated until the low melting point glass layer 103 melts, and then cooled to fix the seven lead frames to the element housing container base 101 .
かかる状態を第7図に示す。同図において104はリー
ドフレームである。かかるリードフレーム−は後に切断
分離され、外部接続端子を構成する。Such a state is shown in FIG. In the figure, 104 is a lead frame. This lead frame is later cut and separated to form external connection terminals.
この工程において素子収容容器基体101上に位置した
リードフレーム104の凸状部105は、カラス層10
3が溶融すると素子収容容器基体101の上面に接する
如くして位置決めされ、凸状部105谷々は同一平面上
に揃つ良状態で素子収容容器基体101上に固着される
。このようなリードフV−ム固看工程においては、ガラ
ス浴融時に電りtリードフン−ムの凸状5105周辺部
にのせ凸状部105/?!r々を素子収容容器基体10
1の表面に押し当てることがoJ能であり、よってリー
ド内端部106各々の上面を同一平面上に確夾に位置出
しすることができる。、リード本数が多い場会にはこの
方法が好ましい。In this step, the convex portion 105 of the lead frame 104 located on the element housing container base 101 is
3 is melted, it is positioned so as to be in contact with the upper surface of the element container base 101, and the convex portion 105 is fixed onto the element container base 101 in a good condition with the valleys aligned on the same plane. In such a lead frame observation process, when the glass bath is melted, an electric current is placed on the periphery of the convex part 5105 of the lead frame. ! element storage container base 10
1. Therefore, the upper surfaces of the inner ends 106 of each lead can be reliably positioned on the same plane. This method is preferable when the number of leads is large.
本発明によれば次いで、前記素子収容部102に半導体
乗積回路素子が収容、固着され、当該半導体集積回路素
子の電極と前記リードフレーム104のリード内端11
106とがアルミニ9ム線等の1IillIIによ夕襞
絖(ワイヤボンディング)される。(かかる状lは図示
せず)かかるワイヤポ7ディフグ処塩工程においては、
前述の如くリード内端部106の各々は同−平向上に位
置して固定されている丸め、自動細4I接続装置等を用
いてのm**aを他めて容易に実施することができる。According to the present invention, next, a semiconductor multiplication circuit element is housed and fixed in the element housing part 102, and the electrode of the semiconductor integrated circuit element and the lead inner end 11 of the lead frame 104 are connected to each other.
106 is wire bonded to 1IillII, such as aluminum 9mm wire. (Such a state l is not shown in the figure) In such a wire po 7 defugu salt treatment process,
As mentioned above, each of the inner ends 106 of the leads are fixedly positioned on the same plane, and m**a can be easily formed using an automatic narrow 4I connecting device or the like. .
一方、前記素子収容容器基体101に対応する太き:5
を有し且つ一方の主面に前記素子収容部102に対応す
る領域食除いて低融点ガラス層が配設され九セラ建ツク
材からなる蓋部材が準備される。かかるfIs材は1s
8図に示されるように前記軍子収容St−檄って配置さ
れ、W記低融点ガラス層の溶融、固化によって素子収容
容器101に園看され、半導体乗積回路素子は気密封止
される。On the other hand, the thickness corresponding to the element storage container base 101 is: 5
A lid member made of a nine-cell construction material is prepared, which has a low melting point glass layer on one main surface except for the area corresponding to the element accommodating portion 102. Such fIs material is 1s
As shown in FIG. 8, the semiconductor integrated circuit device is placed in the device storage container 101 by melting and solidifying the low melting point glass layer, and the semiconductor multiplication circuit device is hermetically sealed. .
第8111!3において10ツは蓋部材を示す。In No. 8111!3, 10 indicates a lid member.
しかる後リードフレーム104は第8図のA−ム′に沿
りて切断され、半導体装置が光取される。Thereafter, the lead frame 104 is cut along line A' in FIG. 8, and the semiconductor device is optically isolated.
なお第9図はM’f図のo−o’断面を示す。Note that FIG. 9 shows an o-o' cross section of the M'f diagram.
このような本発明によれば、1/A子収答谷器基体10
1の索子収容9102の周囲には外部接続端子の凸状部
105が配設され、リードフレームの複数のリード内端
部106はかかる凸状部105によって同−平向上に位
置決めされ良状態で、低融点ガラスによって素子収容容
器基体101に固着される。したがって、前記素子収容
部102に収容される半導体乗積回路素子の電極とリー
ド内端部との閣をワイヤボンディングする際には、かか
るワイヤボンディング作業をすみやかに高い信頼性をも
って実施することができる。According to the present invention, the 1/A child collection device base 10
A convex portion 105 of an external connection terminal is arranged around the cord housing 9102 of No. 1, and the inner ends 106 of the plurality of leads of the lead frame are positioned on the same plane by the convex portion 105 and are in good condition. , is fixed to the element housing container base 101 with low melting point glass. Therefore, when wire bonding is performed between the electrodes of the semiconductor multiplier circuit element housed in the element accommodating section 102 and the inner ends of the leads, such wire bonding work can be carried out quickly and with high reliability. .
なお1以上の実施例にあっては、ガラス層′fr:素子
収容谷器基体の一方の上面の素子収容部を除く全開に配
設したが、尚葭ガラスによる気密特注。In one or more of the embodiments, the glass layer 'fr: The glass layer 'fr' is provided fully open except for the element accommodating portion on one upper surface of the element accommodating valley base, but it is also custom-made airtight with shank glass.
機械的強度等が維持されるものであれば1部分的に配設
してもよい。As long as the mechanical strength and the like are maintained, it may be provided partially.
また外部接続端子に設けられる凸状部も、実施例に示さ
れる形状1位置、形成数に限られるものではない。また
凸状部を素子収容部の周囲全周の外部接続端子金てに配
設してもよい。かかる場曾には、リード本数の少ない部
分のリード内端部にっいても歯該す−ド内港部の位置出
しが容易となる。Further, the number of convex portions provided on the external connection terminals is not limited to one position and number of shapes shown in the embodiments. Further, the convex portion may be provided on the external connection terminal metal all around the periphery of the element accommodating portion. In such a case, it becomes easy to locate the inner port of the tooth even at the inner end of the lead in a portion where the number of leads is small.
なお、藺紀凸状部は半導体素子の固着部近傍に設けられ
るが、これは外S景続端子のリード内端部に半導体孝子
から導出される導体の接続に必要な領域tiI保できる
ような位置に設けられる。Note that the convex part is provided near the fixed part of the semiconductor element, but it is designed so that it can maintain the area tiI necessary for connecting the conductor led out from the semiconductor chip to the inner end of the lead of the external S connection terminal. provided at the location.
*に1本発明の実施例にあっては、デュアルインライン
型票子収容1!器を掲げて説明を行なったが、本発明は
これに限られるものではなく、フラット111素子収容
箒器(いわゆるフラットパッケージ)に対して4過用す
ることができる。*1 In the embodiment of the present invention, dual in-line slip accommodating 1! Although the present invention is explained using a device, the present invention is not limited to this, and can be used for a flat 111 element-accommodating broom (so-called flat package).
偏 −向の簡単なa@
@1−乃至11番図は従来の半導体装置の組み立て工程
の概略を示す外観斜視図及びllili面図であり。Figures 1-1 to 11 are an external perspective view and a top view showing an outline of the assembly process of a conventional semiconductor device.
第5図は本発明による外部接続端子に設けた凸状部の貢
anを示す斜視図、第6図乃至第9図は本発明による半
導体装置の組み立て工程の概略を示す外IIl斜視図及
び断面図である。FIG. 5 is a perspective view showing the structure of the convex portion provided on the external connection terminal according to the present invention, and FIGS. 6 to 9 are external perspective views and cross-sections showing the outline of the assembly process of the semiconductor device according to the present invention. It is a diagram.
図において、l、101・・・・・・素子収容容器基体
、2.102・・・・素子収容部、3,103・・・・
・ガラスMi、4,104・・・・・リードフレーム、
105・・・・・・凸状部、4’、106・・・・・・
リード内端部、5゜101・・・・・・!部材である。In the figure, 1, 101... element housing container base, 2, 102... element housing part, 3, 103...
・Glass Mi, 4,104...Lead frame,
105... Convex portion, 4', 106...
Inner end of lead, 5°101...! It is a member.
犀4図Rhino 4
Claims (1)
され、且つ前記主面上に複数の外部接続端子がガラスに
より固着され、前記半導体素子の電極と前記外部接続端
子とが導電的KW!続されてなる半導体装置において、
前記外filSm続端子には前記半導体素子の固着部近
傍において前記素子収容容器基体に接する如き凸状部が
配設されてなること′f:%黴とする半導体装置。A semiconductor element is mounted on one main surface of the element housing container base, and a plurality of external connection terminals are fixed on the main surface with glass, and the electrodes of the semiconductor element and the external connection terminals are connected to each other by conductive KW. ! In semiconductor devices that are connected
The semiconductor device is characterized in that the outer filSm connection terminal is provided with a convex portion that contacts the element housing container base in the vicinity of the fixed portion of the semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18159681A JPS5882552A (en) | 1981-11-12 | 1981-11-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18159681A JPS5882552A (en) | 1981-11-12 | 1981-11-12 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5882552A true JPS5882552A (en) | 1983-05-18 |
JPH021376B2 JPH021376B2 (en) | 1990-01-11 |
Family
ID=16103569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18159681A Granted JPS5882552A (en) | 1981-11-12 | 1981-11-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5882552A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4626478A (en) * | 1984-03-22 | 1986-12-02 | Unitrode Corporation | Electronic circuit device components having integral spacers providing uniform thickness bonding film |
US4629824A (en) * | 1984-12-24 | 1986-12-16 | Gte Products Corporation | IC package sealing technique |
US4684975A (en) * | 1985-12-16 | 1987-08-04 | National Semiconductor Corporation | Molded semiconductor package having improved heat dissipation |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0675910U (en) * | 1993-04-08 | 1994-10-25 | 小島プレス工業株式会社 | Door lock mechanism for vehicle storage box |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5759367A (en) * | 1980-09-26 | 1982-04-09 | Fujitsu Ltd | Semiconductor container |
-
1981
- 1981-11-12 JP JP18159681A patent/JPS5882552A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5759367A (en) * | 1980-09-26 | 1982-04-09 | Fujitsu Ltd | Semiconductor container |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4626478A (en) * | 1984-03-22 | 1986-12-02 | Unitrode Corporation | Electronic circuit device components having integral spacers providing uniform thickness bonding film |
US4629824A (en) * | 1984-12-24 | 1986-12-16 | Gte Products Corporation | IC package sealing technique |
US4684975A (en) * | 1985-12-16 | 1987-08-04 | National Semiconductor Corporation | Molded semiconductor package having improved heat dissipation |
Also Published As
Publication number | Publication date |
---|---|
JPH021376B2 (en) | 1990-01-11 |
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