JPS5858755A - Static type metal oxide semiconductor memory storage - Google Patents

Abstract

PURPOSE:To reduce the cell area of a static type memory-cell by shaping the internal wiring of the cell by a buried N<+> layer while forming a resistor and VDD wiring in a substrate. CONSTITUTION:A transistor Tr is formed by a V type MOSTr, and the resistor is shaped by high-resistance N type diffusion layers 36, 37 molded into the P type Si substrate 55. Data wires are formed by Al wiring 38, 39, and a MOSTr for a switch is formed by V type MOSTrs 40, 41 using a word 53 shaped by a polycrystal Si layer as a gate. The data wires 38, 39 are electrically connected to N<+> layers 44, 45 shaped to the surface section of the substrate 55 through holes 42, 43 for contact bored to an insulating film. A gate 35' consisting of polycrystal Si of a V type MOSTr 35 is electrically connected to the buried N<+> layer 46 of the substrate 55 through a V-shaped hole, and the internal wiring of the cell is molded by the buried N<+> layers 46, 48 while the resistors 36, 37 and the VDD wiring 49 are formed into the substrate.

Description

[Detailed description of the invention] The present invention relates to a static MOS memory device.

A circuit diagram of a conventional static type M□S memory cell is shown in FIG. A transistor 1.2 forming a flip-flop circuit and a resistor 5 for supplying power thereto.
4 and a word line 9 connected to the gates of switching transistors 7.8 and 7.8 which connect the flip-flops to the tenitor line 5.6. In this memory cell, memory information is stored at nodes 10 and 11. For example, when node 10 is at a high potential, transistor 2 is turned on, so node 11 is at a low potential. It has become. In this state, when the data line 5.6 is set to a high potential and the word line 9 is also set to a high potential to turn the switch transistor 7.8 off, the data is turned off because the transistor 2 is on. Current flows from line 6 through transistor 8.2, whereas no current flows in data line 5 because transistor 1 is in the cut-off state.

When attempting to construct such a circuit using a normal MOS type integrated circuit, 6.4 resistors, 1.8 MO transistors, and 1.4 resistors are required.
2.7.8, since the VDD wiring 12, the V,3 wiring 13, etc. are arranged so as not to overlap with each other, there is a drawback that the area of the cell becomes large.

In order to eliminate these drawbacks, T., J. Rodgcrs et al.
■8S by embedding S LE wiring inside the board
This eliminates the need to form wiring on the substrate surface, reducing the area of the memory cell shown in Figure 1 (IEI=)
・■.

SC-12, Nf15. p., 515 (1977)
)o Figure 2 (j) is a plan view of this memory cell section,
Figure (b) shows the structure taken along the line AA' in Figure (a). The structure of FIG. 2 will be explained below in comparison with the circuit diagram of FIG. 1. The following explanation is for n-channel type MOS
1. Although the description will be made using a lanogistor as an example, the same explanation can be given for a p-channel type.

The transistor 1.2 in FIG. 1 is constituted by a type MO8 transistor 14, 15, and the S8 wiring 13 in FIG. 1 is constituted by a layer 27 buried inside the substrate. The part corresponding to resistance 4 of 11th n] is l~l0 of 1617.
The resistance value of the resistor is controlled by applying an appropriate constant voltage to the polycrystalline silicon gate 25 of the resistor. The 7-ta wire 5.6 in FIG. −(n”
It is electrically connected to the layer filter 2. The switching transistor 7.8 in FIG. 1 is a MOS transistor 20.21 whose gate is a word line 26 formed of polycrystalline silicon.
The n layer of the transistor 1 in FIG. 1, that is, the gate 14' of the ■-type MOS transistor 14, and the source (or train) of the transistor 8, that is, the MOS transistor 21 in FIG. Make an electrical connection by making direct contact between the parts. Similarly,
Transistor 2 of FIG. 1, ie, V-type MO8 transistor 150 gate 15', is transistor 7 of FIG.
That is, it is electrically connected to the source (or train) of the 10S transistor 20 at a portion 22. The vDD wiring 12 in FIG. 1 is constituted by a diffusion layer wiring 24 made of an n layer. In addition, in figure (b), 28
．． 29 is an insulating film, and 63 is a p-type silicon substrate.

In this way, by embedding ■SS wiring inside the substrate5 (by which, the cell area can be reduced by about 30 times compared to the conventional memory cell. However, in this memory cell as well, ■DI) wiring 24, MOS transistor 16.17 corresponding to resistor 6.4 in Fig. 1, V-type MO8) transistor 14.15, switch transistor 20.2
1 etc. must be placed on the substrate surface so that they do not overlap each other.

The present invention provides a static MOS memory cell with a smaller cell area by burying the vDD wiring 12, the resistor 6.4, and the diffusion layer wiring used inside the memory cell in the substrate. It provides:

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 5 is a diagram showing an embodiment of the present invention, in which figure (a) is a plan view, and figures (b), (C), and (d) are respectively A-
A' cross-sectional view, H'-1-3' cross-sectional view, and CC' cross-sectional view. Hereinafter, this embodiment will be explained in comparison with the circuit diagram of FIG. 1.

In FIG. 6, transistor 1.2 of FIG. 1 is replaced by 34.
The resistor 6.4 in FIG. 1 is formed by a high resistance n-swell diffusion layer 56.67 formed in a p-type silicon substrate 55 by ion implantation. The data line 5.6 in FIG.
It consists of V-type MO8) transistors 40 and 41 whose gates are V-type MO8). Further, data lines 38 and 39 are formed on the surface of the p-type silicon substrate 550 through contact holes 42 and 43 made in the insulating film, and are electrically connected to the 0+ layers 44 and 45. Gate 35 made of polycrystalline silicon of V-type MO8) transistor 35 (transistor 2 in FIG. 1)
' is embedded n layer 46 of substrate 55 through V form 54
This n+ layer 46 is electrically connected to the ■ MO8) transistor 34 (7!l) rain diffusion layer and switch ■
40 sources (or drains) of the MO8) run/meta. Similarly, the gate 34' made of polycrystalline silicon of the transistor transistor 4 (transistor 1 in FIG. 35 and the source (or drain) of the switch type MOS transistor 41. In addition, the VDD wiring 12 in FIG.
The n-swelled diffusion layer 36.57 is composed of a DD wiring buried n layer 49 and a wiring n buried layer 46.
Formed between 48 and 48. The v8S wiring 16 in FIG.
A wiring 50 is formed and an n layer 52 is formed through a contact hole 51.
This n-layer 52 serves as a source of a V-type MO transistor 64.35. Note that here, 56 and 57 are insulating films.

In the memory cell of the present invention, as shown in FIG. 6, the internal wiring of the cell is formed of a buried n layer 46, 48, and the resistor 66, 37 and VDD wiring 49 are constructed inside the substrate. In addition, the area of the memory cell is 40 inches smaller than that of a conventional cell, and it is 10 to 1.5 inches larger than a conventional memory cell that uses the ■-type MOS transistor shown in Figure 2 and embeds vS8 wiring inside the substrate. can be made smaller.

As described above, according to the present invention, the cell area of the static memory cell can be made smaller than that of the conventional one, so it is possible to create a static memory integrated circuit with higher integration than the conventional one.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a static MOS memory cell.
FIG. 2(a) is a plan view of a conventional static type MOS memory cell using a conventional ■-type MOS transistor, FIG. 2(b) is a sectional view taken along line A-A' in FIG. Figure 3 (
6(a) is a plan view of a static MOS memory cell of the present invention, and FIGS. 6(b), (C), and (d) are sectional views taken along line A-A' and B-B' in FIG. 6(a), respectively. Cross section, c-c'
FIG. In the figure, 1.2...MOS) transistor, 4...resistance, 5.6...data line 7.
8...MO8) transistor for switch? ...Word line 12...■DD wiring 16...v8S wiring 14.15...V type MO8) U//star 14', 15
'...Polycrystalline silicon gate 16.17...MOS
) Ransistor 18.19...kl wiring 20.21... MO8 for switch) Ransistor 24.
・0 layer 25.26 ・Polycrystal/S1, Congate 27...n
″Buried layer 28.29...Insulating film 60.61・
・Contact hole 32...N+ layer 33...P-type silicon/substrate 64, filter 5...■-type MO8I-lanozister 36.37
...High resistance opening type diffusion layer filter 8.59...AI wiring layer 40.41...■ type MO8) for switch 42
．． 4Ro...Contact hole 44.45...N layer 46...Ro Buried layer 4
7. ■Format 48.49...n Buried layer 50 ・Ae wiring 51 Hole for contact 52
I] Layer 53... Polycrystalline/Lico/Ge-1 54... ■Format 55-1) Form/Lico/Substrate 56.57... Insulating film Patent attorney Junnosuke Nakamura 22 Figures + (11 Go to 2

Claims (1)

[Claims] (1) providing first and second elongated second conductivity type buried layers parallel to each other in a first conductivity type semiconductor substrate; first, second and third bulges each having a tip inserted therein are provided from one end to the other end of each of the first and second second conductivity type buried layers;
A first insulating film is formed on the substrate surface portion from the periphery of the first ① bulge on the first second conductivity type buried layer to the periphery of the second V bulge on the second second conductivity type burying layer. an insulating film within the first V bulge on the first second conductivity type buried layer and the second □ bulge on the second second conductivity type buried layer; By providing first and second V-shaped metal electrodes respectively through the first and second second conductivity type buried layers, the first and second conductivity type layers and the first and second V-shaped metal electrodes, first and second V-shaped metal electrodes as drain, north and gate electrodes, respectively;
408) In addition to configuring a lanogistor, the substrate part indirectly forms the second conductive layer within the first bulk on the second buried layer of the second conductive type through the second conductive type layer. The conductivity type buried layer directly connects the substrate and the second
A first lead-out V-shaped metal electrode connected to the conductivity type buried layer is connected to the second conductivity type buried layer on the first second conductivity type buried layer.
■ A second conductive layer that is connected indirectly to the substrate portion through the second conductivity type layer and directly to the substrate and the first second conductivity type buried layer in the second conductivity type buried layer. V-shaped metal electrodes for extraction are provided, and the first and second V-shaped metal electrodes for extraction and the first and second ■-shaped MO8 are provided.
) each of the gate electrodes of the Lanozister is connected to an electric cup through a highly conductive film provided on the substrate via an insulating film; (2) A second conductivity type buried layer is provided in the substrate on the form side, and is perpendicular to and spaced apart from the first and second second conductivity type buried layers; A high-resistance second conductivity type layer connecting each of the buried layers and the third second conductivity type buried layer is provided, and the third conductivity type layer is provided on each of the first and second second conductivity type buried layers. second and sixth second conductivity type layers on the surface of the substrate from the periphery of the V type to the sixth second conductivity type buried layer; The third and fourth V-shaped metal electrodes are provided in the third V-bulk above each of the buried layers through an insulating film, thereby forming the first and second second conductivity type buried layers. , constitute sixth and fourth V-type MO8 transistors in which the second and sixth second conductivity type layers and the third and fourth V-type metal electrodes serve as source, drain, and sixth gate electrodes, respectively. At the same time, the gate electrodes of the 4OS transistors are electrically connected to the sixth and fourth V-types by a highly conductive film provided on the substrate via an insulating film, and the third second conductivity type buried layer is formed. the second and sixth second at the top;
From above each of the barrel electroform layers, the first layer is inserted through the insulating film.
and first and second metal film wirings extending in respective directions of the second second conductivity type buried layer, and the first metal film wiring extending in the respective directions of the second second conductivity type buried layer, and the first metal film wiring extending in the respective directions of the second second conductivity type buried layer. Static type MOS memory device-0 characterized in that a sixth metal film wiring is provided extending in parallel to the first and second metal film wiring from above the second conductivity type layer via an insulating film.