JPS5856537A - Reception circuit - Google Patents
Reception circuitInfo
- Publication number
- JPS5856537A JPS5856537A JP56154617A JP15461781A JPS5856537A JP S5856537 A JPS5856537 A JP S5856537A JP 56154617 A JP56154617 A JP 56154617A JP 15461781 A JP15461781 A JP 15461781A JP S5856537 A JPS5856537 A JP S5856537A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- level
- output
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
- H04B10/6931—Automatic gain control of the preamplifier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/691—Arrangements for optimizing the photodetector in the receiver
- H04B10/6911—Photodiode bias control, e.g. for compensating temperature variations
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Optical Communication System (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、タイミング成分を一定にする符号化形式の信
号のタイミング成分をモニタしつ\自動利得制御をなす
受信回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit that performs automatic gain control while monitoring the timing component of a coded signal that keeps the timing component constant.
従来の光受信回路における入力信号のレベル変動に対処
するための自動利得制御形式は、第1図に示すように、
等化器(])の出方にビーク検出回路(2)を設けその
出方信号に応答する自動利得制御回路(3)から受光素
子(4)、増幅器(ωへ自動利得制御信号を供給してそ
れぞれの利得を調整する如きものであった。この自動第
1得制御回路はその構成からも明らかなように、入力信
号はその符号化形式の如何を問わず、動作しうるもので
あるが、混入されている鍵音成分の影響が強く現われ、
自動オリ得制御の安定度が劣る外、回路構成が複雑にな
るというデメリットがめる。The automatic gain control format for dealing with input signal level fluctuations in conventional optical receiving circuits is as shown in Figure 1.
A beak detection circuit (2) is provided at the output side of the equalizer (2), and an automatic gain control circuit (3) that responds to the output signal supplies an automatic gain control signal to the light receiving element (4) and the amplifier (ω). As is clear from its configuration, this automatic first gain control circuit can operate regardless of the encoding format of the input signal. , the influence of the mixed key tone components appears strongly,
The disadvantages are that the stability of the automatic balance control is poor and the circuit configuration is complicated.
第1図において、(6)はタイミング再生回路、(7)
は識別回路である。In Figure 1, (6) is a timing recovery circuit, (7)
is an identification circuit.
本発明は入力信号が符号化される符号化形式に着目して
創案されたもので、その目的は入力信号のタイミング成
分の一定性を活用して成シ、自動利得制御の安定度が優
れており、しかも回路構成を簡易化しうる受信回路を提
供することにある。The present invention was created by focusing on the encoding format in which the input signal is encoded, and its purpose is to utilize the constancy of the timing component of the input signal to improve the stability of automatic gain control. The object of the present invention is to provide a receiving circuit which has a simple circuit configuration.
以下、添付図面を参照して本発明の一実施例を説明する
。Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.
第2図は本発明の実施例回路を示し、顛は受光素子、0
は増幅器でこれらにより入力回路軸を構成する。この入
力回路a3は利得制御入力を有する。受光素子aQには
、タイミング成分を一定にする符号化形式、例えばIB
ITで符号化されて伝送されて来九光信号が照射される
。受光素子aIJの出力信号は増幅器・Dlそして等化
量αjを経て識別回路a4へ供給される。この識別回路
α4は後述するタイミング信号を受けて等化量峙の出力
信号からデータ信号を発生するように構成されている。FIG. 2 shows an embodiment circuit of the present invention, in which the photodetector, 0
are amplifiers, and these constitute the input circuit axis. This input circuit a3 has a gain control input. The light-receiving element aQ has an encoding format that makes the timing component constant, for example, IB.
It is encoded and transmitted by IT, and nine optical signals are emitted. The output signal of the light receiving element aIJ is supplied to the identification circuit a4 via an amplifier Dl and an equalization amount αj. This identification circuit α4 is configured to receive a timing signal to be described later and generate a data signal from an output signal corresponding to the equalization amount.
入力回路−の出力にはレベル検出回路手段−が接続され
ている。この回路手段は、増幅器■の出力へ接続された
狭帯域通過フィルタ顛と、フィルタa@の出力に接続さ
れたリミット増幅器−ηと、該増幅器のレベル検出用出
力へ接続され九検出回路舖とから成る。IJ ミツト増
幅器1カは上記出力の外、識別回路a◆へ供給されるタ
イミング信号、並びにバイポーラ出力を発生し、且つ同
期をとるためのクロック信号(CLK)の各出力を有す
るー。また、検出回路α蹄の入力はフィルタaQの出力
へ接続されてレベル検出回路手段O噴が構成されてもよ
い。A level detection circuit means is connected to the output of the input circuit. This circuit means includes a narrow band pass filter connected to the output of the amplifier (1), a limit amplifier -η connected to the output of the filter (a), and a nine detection circuit (9) connected to the level detection output of the amplifier. Consists of. In addition to the above-mentioned outputs, the IJ Mitsu amplifier has a timing signal supplied to the identification circuit a◆, and a clock signal (CLK) for generating and synchronizing bipolar output. Further, the input of the detection circuit α may be connected to the output of the filter aQ to constitute the level detection circuit means O.
レベル検出回路手段(2)の出力は自動利得制御回路6
1へ接続され、該回路の出力は入力回路0の利得制御入
力へ接続されている。The output of the level detection circuit means (2) is the automatic gain control circuit 6.
1 and the output of the circuit is connected to the gain control input of input circuit 0.
次に1上記構成の本発明回路の動作を説明する。Next, the operation of the circuit of the present invention having the above configuration will be explained.
タイミング成分を一定にする符号化方式、例えばIBI
T符号化方式で符号化された光信号が受光素子(if)
で受光され、増幅6儀υで増幅される。増幅器Iの出力
信号は等化量輪を通過された後、識別回路α4でリミッ
ト増幅器Q7)からのタイミング信号を受けつ\識別さ
れてデータ信号を直列的に出力する。Encoding methods that keep timing components constant, such as IBI
The optical signal encoded using the T encoding method is transmitted to the light receiving element (if)
The light is received by the amplification device υ and amplified by the amplification device υ. The output signal of the amplifier I is passed through an equalization ring, and then received and identified by the identification circuit α4 by the timing signal from the limit amplifier Q7), and outputs a data signal in series.
このようなデータ信号の受信中に、光信号のレベルが変
動するとき、入力回路軸へ自動利得制御回路0から自動
利得制御信号が供給されて、入力回路υの出力レベルを
一足に保つように動作する。When the level of the optical signal fluctuates while receiving such a data signal, an automatic gain control signal is supplied from automatic gain control circuit 0 to the input circuit axis to keep the output level of the input circuit υ constant. Operate.
この自動利得制御回路a1への制御入力信号は、入力回
路的の出力信号の内のタイミング成分が狭帯域通過フィ
ルタa輪を通過され、リミット増幅6翰からそのタイミ
ング成分レベルが発生され、このレベルがレベル検出器
α樟に予め設定されている設定レベルに対し、高いか又
は低いかに従ってこれを表れず信号がレベル検出器軸か
ら発生されて供給される。The control input signal to this automatic gain control circuit a1 is obtained by passing the timing component of the output signal of the input circuit through a narrow band pass filter A, and generating the level of the timing component from the limit amplifier 6. A signal is generated and supplied from the level detector shaft, depending on whether the signal is higher or lower than the set level preset in the level detector α.
このような自動利得制御系は、そのレベル検出口路手段
口[有]に狭帯域通過フィルタaQを設けて雑音成分の
タイミング成分からの分離をもなしているので、自動利
得制御の安定度が良り、そして、このような効果は従来
回路に比して回路構成を簡易にして得られる。Such an automatic gain control system is provided with a narrow band pass filter aQ at its level detection port to separate the noise component from the timing component, so the stability of the automatic gain control is improved. This effect can be obtained by simplifying the circuit configuration compared to conventional circuits.
上記実施例においては、光信号を受信する場合について
述べたが、本発明がこれに限定されるものでないことは
その要旨から明らかであり、その他の、同種符号化形式
で符号化された信号の受信にも適用しうるものである。Although the above embodiment describes the case where an optical signal is received, it is clear from the gist that the present invention is not limited to this, and it is clear that the present invention is not limited to this. This can also be applied to reception.
以上の説明から明らかなように、本発明によれば次のよ
うな効果が得られる。As is clear from the above description, the following effects can be obtained according to the present invention.
■ 自動利得制御の安定度が良い。■ Good stability of automatic gain control.
■ 回路構成が簡易になる等である。■ The circuit configuration becomes simpler.
第1図は従来回路図、第2図は本発明回路図でおる。
図中、a3は入力回路、aコはレベル検出回路手段、a
lは自動利得制御回路である。
特許出願人 富士通株式会社FIG. 1 is a conventional circuit diagram, and FIG. 2 is a circuit diagram of the present invention. In the figure, a3 is an input circuit, a is a level detection circuit means, a
1 is an automatic gain control circuit. Patent applicant Fujitsu Limited
Claims (2)
号化された信号を入力回路に受け、該入力回路の出力に
接続されたレベル検出回路手段で上記信号のタイミング
信号成分をモニタしそのモニタ出力信号に応答して上記
入力回路に自動利得制御信号を供給するように構成した
ことを特徴とする受信回路。(1) An input circuit receives a signal encoded using an encoding method that makes the timing component constant, monitors the timing signal component of the signal using level detection circuit means connected to the output of the input circuit, and outputs the monitor output. A receiver circuit configured to supply an automatic gain control signal to the input circuit in response to a signal.
タを含めて構成されたことを特徴とする特許請求の範囲
第1項記載の受信回路。(2) The receiving circuit according to claim 1, wherein the level detection circuit means includes a narrow band pass filter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56154617A JPS5856537A (en) | 1981-09-29 | 1981-09-29 | Reception circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56154617A JPS5856537A (en) | 1981-09-29 | 1981-09-29 | Reception circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5856537A true JPS5856537A (en) | 1983-04-04 |
Family
ID=15588092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56154617A Pending JPS5856537A (en) | 1981-09-29 | 1981-09-29 | Reception circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856537A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2669167A1 (en) * | 1990-11-12 | 1992-05-15 | Neiman Sa | Infrared signal receiver circuit and remote control assembly employing such a circuit |
KR100890293B1 (en) * | 2004-08-18 | 2009-03-26 | 로무 가부시키가이샤 | Gain adjustment circuit, signal processing circuit, and electric device |
-
1981
- 1981-09-29 JP JP56154617A patent/JPS5856537A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2669167A1 (en) * | 1990-11-12 | 1992-05-15 | Neiman Sa | Infrared signal receiver circuit and remote control assembly employing such a circuit |
KR100890293B1 (en) * | 2004-08-18 | 2009-03-26 | 로무 가부시키가이샤 | Gain adjustment circuit, signal processing circuit, and electric device |
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