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JPS5851528A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5851528A
JPS5851528A JP15015981A JP15015981A JPS5851528A JP S5851528 A JPS5851528 A JP S5851528A JP 15015981 A JP15015981 A JP 15015981A JP 15015981 A JP15015981 A JP 15015981A JP S5851528 A JPS5851528 A JP S5851528A
Authority
JP
Japan
Prior art keywords
substrate
pattern
defect
light
pseudo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15015981A
Other languages
Japanese (ja)
Other versions
JPS612296B2 (en
Inventor
Osami Ban
伴 修実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15015981A priority Critical patent/JPS5851528A/en
Publication of JPS5851528A publication Critical patent/JPS5851528A/en
Publication of JPS612296B2 publication Critical patent/JPS612296B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To inspect a pattern formed onto a dummy substrate by scanning the upper section of the substrate, to which the pattern is shaped, by two rays and detecting the difference of beams transmitting the substrate. CONSTITUTION:The same pattern sections of two adjacent elements among the patterns formed to the surface of the dummy substrate 11 are each scanned simultaneously by two minute spotty rays projected from a light source 13. Beams transmitting the substrate 11 are each received by means of photomultipliers 15, 15', converted into electrical signals corresponding to the intensity of transmitted light, amplified by means of picture amplifiers 16, 16' and transmitted to a differential amplifier 17. When the pattern of one element has a defect, two input of the amplifier 17 do not agree. A CPU 14 detects the defect by the output value of the amplifier 17, and transmits a signal indicating the defect to a printer 18 and a video monitor 19.

Description

【発明の詳細な説明】 本発明は半導体装置の斃造方法に−し、特にパターン形
成工程における不良検出方法に−する、半導体装置を製
造するには、周知の如く半導体基#R#ζパターン形成
工程が繰り返し施ζされ、各1のパターンが半導体基板
上に形成される。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for detecting defects in a pattern forming process. The forming process is repeated to form each pattern on the semiconductor substrate.

上記半導体基板上に形成されるパターンは、例えば拡散
工程のマスク層として用いられる二酸化シリコン(8i
偽) II、イオン注入工程のマスク触として用いられ
るホトレジスト族、半導体基板の所定領tjkIiIを
電気的に接続する配線、或いはこれらを形成するための
ホトリソグラフィ工程においてマスク層として用いられ
る本トレジスト膜等多岐にわた9ている。
The pattern formed on the semiconductor substrate is, for example, silicon dioxide (8i
False) II, a photoresist family used as a mask contact in the ion implantation process, a wiring that electrically connects a predetermined area of a semiconductor substrate, or a photoresist film used as a mask layer in the photolithography process to form these, etc. There are 9 different types.

半導体装置の製造歩留及び徊軸夏を向上させるiζは、
上記各麺パターンが欠陥のないものであることか必装で
ある。そこでパターンの不良発生線内を除去するため、
形成されたパターンの検量か行なわれる。ところか昨今
のLSI、超LSIのような半導体に激においては、パ
ターンは微細化され且つ為INIt化されているため、
形成されたすべてのパターンを検査することは到低不可
能で、波数り1M量によらさるを得ないか、この抜取検
査の試料数をたとえ数10業子程良としても多大の検量
工数を製するにも拘らず、欠陥検出力は十分とは1い麺
い。
iζ, which improves the manufacturing yield and rotational speed of semiconductor devices, is
It is essential that each noodle pattern mentioned above be free of defects. Therefore, in order to remove the defective lines in the pattern,
The formed pattern is then calibrated. However, in recent times, in semiconductors such as LSI and VLSI, patterns have become finer and INIt.
It is extremely impossible to inspect all the formed patterns, and it is inevitable that the number of waves is 1M, or even if the number of samples for this sampling inspection is several tens of days, it will require a large amount of calibration man-hours. Despite the fact that it is manufactured by a manufacturer, its ability to detect defects is still insufficient.

そCで本発明の目的はパターン検査の欠陥m出力を向上
させるためパターンの自yIIJ検査を可能ならしめる
半導体装置の製造方法を提供することにあり、そのため
本発明は、半導体IkIl&と共に、光を透過し得る材
料よりなる疑似基板に対してパターン形成工程を施仁し
、しかる鶴前記疑似基板を光線により走査し、透過光を
検知すること番こより前記疑似基板上に形成されたパタ
ーンを検査する工程を含むことを特徴とする。
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that enables pattern self-yIIJ inspection in order to improve the defect m output of pattern inspection. A pattern forming process is performed on a pseudo substrate made of a transparent material, and the pattern formed on the pseudo substrate is inspected by scanning the pseudo substrate with a light beam and detecting the transmitted light. It is characterized by including a process.

以下本発明の一実施例を図面番こより説明する。An embodiment of the present invention will be described below with reference to the drawing numbers.

#11図は上記一実施例に用いた石英よりなる疑似基板
の上山図で、lは使用する半導体基板とほぼ同一寸法に
作成された石英基板、2は半導体素子14Illに対応
する区域i示し、この中に複数のパターンが形成される
Figure #11 is a top view of a pseudo-substrate made of quartz used in the above embodiment, l indicates a quartz substrate made to have almost the same dimensions as the semiconductor substrate used, 2 indicates an area i corresponding to the semiconductor element 14Ill, A plurality of patterns are formed in this.

第2〜は本発明の一実施例を工程の順に示す要部断面図
でありて、アルミニウム(ムl)よリナル配パターン形
成工程を掲げて説明する。
2 to 2 are sectional views of essential parts showing an embodiment of the present invention in the order of steps, and the step of forming a linal pattern using aluminum (mul) will be explained.

−図(相こおいて、lは前述の石英基板である。- Figure (In this figure, l is the aforementioned quartz substrate.

ンIζ従りてホトレジスト膜4を形成する。次いで仁の
ホトレジスト膜4をマスクとしてhtHBを過択的番ζ
除去した彼、本トレジスト&iI4を除去して、11k
(b)に見られるよう曇こ所定のパターンを有するMk
線6か形成される。以1の工程はすべて半導体装置を形
成するための半導体1に板と共に施こされるもので、通
常の製造工程と何ら変る点はない。
Then, a photoresist film 4 is formed. Next, using the photoresist film 4 as a mask, htHB was selectively applied to ζ.
Removed him, removed book resist & iI4, 11k
Mk with a cloudy predetermined pattern as seen in (b)
Line 6 is formed. All of the following steps are performed on the semiconductor 1 together with the plate for forming a semiconductor device, and there is no difference from the normal manufacturing process.

11V((+)はパターンの欠陥の例を示すもので、6
はルの残量、7はピンホールを示す。これらは昨今の半
導体装置においてはいずれも徹細なものであって、k4
1k鏡を用いて拡大しても発見するのは容易ではない。
11V ((+) indicates an example of a pattern defect, 6
7 indicates the remaining capacity, and 7 indicates a pinhole. All of these are detailed in recent semiconductor devices, and k4
Even when magnified using a 1k mirror, it is not easy to find.

18図は上述のように作成した疑似基板のパターン検量
方法及び使用した桜食装振を示すシステム構成図である
FIG. 18 is a system configuration diagram showing the pattern calibration method for the pseudo-substrate created as described above and the Sakura Shokusoshin used.

この検査装置はマスターマスク等の検査用として一般に
市販されている透過型のマスク自動検査装置でありて、
徽細な欠陥であ2てもi/l1i1に検出し得るもので
ある0本発明の目的は換Bすれは、この極の検査装置を
用いて半導体装置の製造工程中に形成されたパターンの
検査をなし得るようにすること−こある。ただ上述の検
査装置は透過型のため、半導体基板上に形成されたパタ
ーンを自接検査する仁とは不可能である。そこで半導体
&板上Iζパターンを形成する除曇こ、同一条件下で、
光を透過し得る基板上に同一パターンを形成する。
This inspection device is a transmission type automatic mask inspection device that is generally commercially available for inspection of master masks, etc.
The purpose of the present invention is to detect patterns formed during the manufacturing process of semiconductor devices using this type of inspection equipment. To make it possible to carry out inspections. However, since the above-mentioned inspection apparatus is of a transmission type, it is impossible to directly inspect patterns formed on a semiconductor substrate. Therefore, under the same conditions, the defogging process that forms the Iζ pattern on the semiconductor and board,
The same pattern is formed on a substrate that can transmit light.

このように作成された&似基板を前述のマスク自lE!
l検査装重で検査することにより、稍度の高いデータか
大量に且つ容易に得られる。従って当該工程における欠
陥の発生状況を適確に把握できることとなる。
The above-mentioned mask is used for the &similar board created in this way!
By testing with 1 test equipment, a large amount of highly accurate data can be easily obtained. Therefore, the occurrence of defects in the process can be accurately grasped.

次に上記検査装置の動作を簡単に説明する。Next, the operation of the above inspection device will be briefly explained.

第8図に見られる如く、疑似基板llを支持台12上に
散散する。この疑似基板11表−に形成されたパターン
のうちlI!接する2つの素子(抛示せず)の同一パタ
ーン部分を、それぞれに光fi18より投射された2本
の微小スポット状の光線により同時暑こ走査する。上記
2本の光線は、光源18内部に設けられた陰1i11i
1(DR↑)のスクリーンの所定部分を発光せしめ、仁
の光をレンズ糸により集光し、分岐して験体表面に結像
せしめたものである。従って験体表向の走査は、上記C
RTのスクリーン上の発光位置を中央処理装置11(C
PU)14により制御することによって行なうことがで
き、またその際2本の光線は完全に同期して掃引される
As shown in FIG. 8, the pseudo substrates 11 are scattered on the support stand 12. Of the patterns formed on this pseudo substrate 11, lI! The same pattern portions of two adjacent elements (not shown) are simultaneously scanned by two minute spot-shaped light beams projected from the light fi 18. The above two light rays are transmitted through a shade 1i11i provided inside the light source 18.
A predetermined portion of the screen No. 1 (DR↑) is made to emit light, and the light is focused by a lens thread, branched, and formed into an image on the surface of the subject. Therefore, the scanning on the surface of the experiment is
The central processing unit 11 (C
(PU) 14, the two beams being swept in perfect synchronization.

このようにし投射され、Wk似基板11を透過した光は
、それぞれホトマルチプライヤ151.1gで受光され
、透過光強度に対応した電気信号に変換され、vlk録
増−器16.16により増幅されて差動増幅−17に送
られる。この両者は1IIi&する2つの素子の向一部
分のパターンの有無に対応しているので、上記2つのパ
ターンかいずれも正常であれば上記2つの信号波形はけ
ば同一となる。従って差動増幅1!17の出力はほぼセ
ロとなる。
The light projected in this manner and transmitted through the WK-like substrate 11 is received by a photomultiplier 151.1g, converted into an electrical signal corresponding to the intensity of the transmitted light, and amplified by a VLK recorder 16.16. and sent to differential amplifier -17. Since both of these correspond to the presence or absence of a pattern on the opposite part of the two elements that perform 1IIi&, if either of the above two patterns is normal, the two signal waveforms will be the same. Therefore, the output of the differential amplifier 1!17 becomes almost zero.

これ−ζ対し、−万の素子のパターンが前記1h810
に示すような欠陥を有するときは、ピンホール7におい
ては光か透過し、′!jc渣6Iこお5いては遮光され
るので、差動増幅617の2つの入力は一致しない。従
りて差動増1!6!に17はIJa者の差に相当する出
力を逸出する。
For this -ζ, the pattern of -10,000 elements is 1h810
When there is a defect as shown in , some light is transmitted through the pinhole 7, and '! Since the jc signal 6I is shielded from light, the two inputs of the differential amplifier 617 do not match. Therefore, the differential increase is 1!6! 17 emit an output corresponding to the difference between the IJa users.

CP 1:l 14は入力された差動増ll1l器17
の場カの値により欠陥を極用い欠陥を示を信号をその位
敏l&橡と共にプリンタ18やビデオモニタ19に送出
し、曲記疑似基板11を示す図形(例えは第1図に示す
ような図形)上に欠陥を表示せしめる。
CP 1:l 14 is the input differential amplifier ll1l 17
A signal indicating the defect is sent to the printer 18 or video monitor 19 along with the value of the field force, and a figure indicating the pseudo board 11 (for example, as shown in FIG. 1) is sent. display the defect on the figure).

上記一連の操作をCP U 14からの指令に基き、支
持台駆動回路20を作動せしめて支持台を一次移動させ
ることにより、疑似基板ll上のすべてのパターンにつ
いて繰り返す。このようにして疑似基板11全向にわた
りて欠陥を正確且つ迅速に検出することができる。
The above series of operations is repeated for all patterns on the pseudo substrate 11 by activating the support stand drive circuit 20 and moving the support stand based on a command from the CPU 14. In this way, defects can be detected accurately and quickly in all directions of the pseudo substrate 11.

本実h’lkによればパターンの検査はすべて自動的に
行なわれるので、大魚のデータが得られるので欠陥の検
出力が高まり、しかも上Ie検倉はインライン検査とな
し得るので、パターン形成工程の状態を過龜且つ速やか
に把握することができ、従って同工程に対する改も活動
を迅速且つ適切に行なうことかTiJ能となる。
According to Honjitsu h'lk, all pattern inspections are performed automatically, so large-scale data can be obtained, increasing the ability to detect defects.Furthermore, the upper Ie inspection can be done as an in-line inspection, so the pattern forming process can be carried out automatically. It is possible to grasp the status of the process quickly and quickly, and therefore it becomes possible to quickly and appropriately carry out activities to improve the same process.

なお前記Ik(1!基板の材質は石英に限らす、カラス
、跋いはサファイア等光を′il!l過するものの中か
ら選択して良い。また本発明を東施し得るパターン形成
工程は配線パターンの形成工程に限定されるものではな
く、基板上に皮膜を被着せしめ、次いでこれをバターニ
ングする工程であればいかなるパターン形成工程であり
てもよい。
The material of the Ik (1!) substrate is limited to quartz, and may be selected from materials that transmit light, such as quartz and sapphire.The pattern forming process in which the present invention can be applied is the wiring. The present invention is not limited to a pattern forming process, and may be any pattern forming process as long as it is a process of depositing a film on a substrate and then patterning it.

また前記一実施例においては照射される光線として可視
光を用いたが、これは疑似基板は透過し、疑似基板1番
こ形成されたパターンは透過しないものであればよく、
紫外光、赤外光等を用いることも可能である。
In addition, in the above embodiment, visible light was used as the irradiated light, but it is sufficient that the visible light passes through the pseudo substrate but does not pass through the pattern formed on the pseudo substrate.
It is also possible to use ultraviolet light, infrared light, etc.

以上説明した如く本発明によれば、パターン形成工程の
欠陥発生状況及びその原因等に胸する情報か適確且つ迅
速に得られるので、半導体製電の製造歩留及び伽幀度か
向上する。
As described above, according to the present invention, information regarding the occurrence of defects in the pattern forming process and their causes can be obtained accurately and quickly, thereby improving the manufacturing yield and reliability of semiconductor electrical manufacturing.

【図面の簡単な説明】[Brief explanation of drawings]

j@1図及び第21は本発明の一実施例の疑似基板を示
す上曲図及び要部11r面h1亀81は上記−実1m@
のパターン検査方法及び使用した検査装置を示すシステ
ム11&図である。 1において、lは光をa過し得る材料よりなる基板、5
は形成されたパターン、6.7は欠陥、llは疑似基板
を示す。
Figure 1 and Figure 21 are upper curved views showing a pseudo board according to an embodiment of the present invention, and the main part 11r surface h1 turtle 81 is the above-actual 1m@
It is a system 11 & diagram showing a pattern inspection method and an inspection device used. 1, l is a substrate made of a material that can transmit a light; 5
6.7 indicates a formed pattern, 6.7 indicates a defect, and 11 indicates a pseudo substrate.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板にパターン形成工程を施こすに際し、前記半
導体基板と共に光を透過し得る材料よりなる疑似基板−
と前記パターン形成工程を施こし、しかる後゛前記疑似
基板上を光線により走査し、齢記疑似基板を透過せる光
を検知することにより前記疑似基板上に形成されたパタ
ーンを検査する工程を含むことを特徴とする半導体装置
の製造方法。
When performing a pattern forming process on a semiconductor substrate, a pseudo substrate made of a material that can transmit light together with the semiconductor substrate.
and performing the pattern forming step, and then inspecting the pattern formed on the pseudo substrate by scanning the pseudo substrate with a light beam and detecting the light that can be transmitted through the pseudo substrate. A method for manufacturing a semiconductor device, characterized in that:
JP15015981A 1981-09-22 1981-09-22 Manufacture of semiconductor device Granted JPS5851528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15015981A JPS5851528A (en) 1981-09-22 1981-09-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15015981A JPS5851528A (en) 1981-09-22 1981-09-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5851528A true JPS5851528A (en) 1983-03-26
JPS612296B2 JPS612296B2 (en) 1986-01-23

Family

ID=15490787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15015981A Granted JPS5851528A (en) 1981-09-22 1981-09-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5851528A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921037A (en) * 1982-07-26 1984-02-02 Nec Corp Monitoring method for pattern of semiconductor device
JP2008140671A (en) * 2006-12-04 2008-06-19 Matsushita Electric Ind Co Ltd Switch device, and remote control transmitter using the same
JP2008140672A (en) * 2006-12-04 2008-06-19 Matsushita Electric Ind Co Ltd Switch device, and remote control transmitter using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921037A (en) * 1982-07-26 1984-02-02 Nec Corp Monitoring method for pattern of semiconductor device
JP2008140671A (en) * 2006-12-04 2008-06-19 Matsushita Electric Ind Co Ltd Switch device, and remote control transmitter using the same
JP2008140672A (en) * 2006-12-04 2008-06-19 Matsushita Electric Ind Co Ltd Switch device, and remote control transmitter using the same

Also Published As

Publication number Publication date
JPS612296B2 (en) 1986-01-23

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