JPS5846626A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5846626A JPS5846626A JP56145235A JP14523581A JPS5846626A JP S5846626 A JPS5846626 A JP S5846626A JP 56145235 A JP56145235 A JP 56145235A JP 14523581 A JP14523581 A JP 14523581A JP S5846626 A JPS5846626 A JP S5846626A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon dioxide
- silicon
- dioxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関するものτあり、特
式絶縁談上に単結晶シリコン膜を形成する方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a single crystal silicon film on a special insulation board.
レーデ光、７うＶシ異光、電子ビーム、イオンビーム岬
を牛導体表面に短時間照射して熱処理を行なう技術であ
るビームアニール技術は絶縁膜上の多結晶シリコン膜上
に単結晶を成長させる工程にも用いられる。Beam annealing technology is a technology that performs heat treatment by irradiating the surface of a conductor with LED light, 7V radiation, electron beam, or ion beam for a short period of time to grow a single crystal on a polycrystalline silicon film on an insulating film. It is also used in the process of
上記絶縁膜上の多結晶シリコン膜上に単結晶を成長させ
る工程は紺１ｗＪに示されるように半導体基板１上に例
えば二酸化シリコン尋の絶縁Ｍ２を＼
形威し次に該絶縁膜２上に多結晶シリコンｌ［３を形成
し、この多結晶シリコン膜をビームアニールし、多結晶
シリコン膜表面を単結晶化せしめるのであるが従来ビー
ムアニール工程の際に１ＳＷｓ縦の！１いエネルギーで
単結晶化を行なうと絶縁膜２と多結晶シリコンＨ３との
間の境界面４で多結晶シリコンの剥離が発生する。また
１１度勾配によシ多結晶シリコン３にも亀裂が発生する
。また多結晶シリコンの剥離を発生させないためにビー
ム・アニールのエネルプーを弱めて行なうとｇｙａｉｎ
サイズの大きな単結晶を得ることが出来ない。また従来
の方法で＃ｉ得られた単結晶の表面（多結晶シリコン３
の表面５の部分）が波形となる。このような形状は素子
製造の点で問題となる。The step of growing a single crystal on the polycrystalline silicon film on the insulating film is to form an insulating layer M2 of, for example, silicon dioxide on the semiconductor substrate 1, and then to grow a single crystal on the insulating film 2, as shown in FIG. Polycrystalline silicon l[3 is formed and this polycrystalline silicon film is beam annealed to make the surface of the polycrystalline silicon film single crystallized. Conventionally, during the beam annealing process, 1SWs vertical! If single crystallization is performed with a low energy, polycrystalline silicon will peel off at the interface 4 between the insulating film 2 and the polycrystalline silicon H3. Also, cracks occur in the polycrystalline silicon 3 due to the 11 degree slope. Also, in order to prevent the polycrystalline silicon from peeling off, the energy of the beam annealing may be weakened.
It is not possible to obtain large single crystals. In addition, the surface of single crystal #i obtained by the conventional method (polycrystalline silicon 3
surface 5) has a waveform. Such a shape poses a problem in terms of device manufacturing.
そこで本発明は上記欠点を解消して絶縁膜上にｇｒａｉ
ｎサイズの大きな良質の単結晶領域を形成することを目
的とする。Therefore, the present invention solves the above-mentioned drawbacks and provides a grai layer on the insulating film.
The purpose is to form a high quality single crystal region with a large n size.
本発明の目的は半導体基板上に、絶縁膜を形成し、次に
該絶縁膜上に多結晶シリコン膜を形成して次に１多結晶
シリコン膜をビームアニールすることによって単結晶シ
リコン膜を形成する工程を含む半導体装置の製造方法に
おいて、前記多結晶シリコン膜を形成し圧抜、該多結晶
シリコン膜上に二酸化シリコン膜を形成し、単結晶形成
部に相当する該二酸化シリコン膜を工Ｖチンダによシ除
去し次に光を透過し且つキャップ効果を有する被覆材を
被覆し圧抜に前記多結晶シリコン膜をアニールすること
を特徴とする半導体装置の製造方法によって達成される
。すなわち本発明は単結晶のｇｒａｆＩＩサイズの拡大
は単結晶化の周辺領域が自由端にならなけれは寮現され
ないため従来欠点であった多結晶シリコンの剥離を利用
し、且つ光を透過するキャｙ７”効果を有するを被讃せ
しめることを＊＊とするものである＠
以下本発明を１！施例に基づいて説明する。The purpose of the present invention is to form an insulating film on a semiconductor substrate, then form a polycrystalline silicon film on the insulating film, and then form a single crystal silicon film by beam annealing one polycrystalline silicon film. In the method of manufacturing a semiconductor device, the method includes the steps of forming the polycrystalline silicon film, releasing the pressure, forming a silicon dioxide film on the polycrystalline silicon film, and removing the silicon dioxide film corresponding to the single crystal formation portion by a V-etching process. This is achieved by a method of manufacturing a semiconductor device, which is characterized in that the polycrystalline silicon film is removed by tinkering, then coated with a coating material that transmits light and has a capping effect, and then annealed to release the pressure. In other words, the present invention takes advantage of the exfoliation of polycrystalline silicon, which has been a drawback in the past, since the enlargement of the graf II size of a single crystal cannot be realized unless the peripheral region of the single crystal becomes a free end, and also utilizes the exfoliation of polycrystalline silicon, which transmits light. The present invention will be described below based on 1!Example.
＃１２図ないし館５図は本発明に係る飴縁膜上に単結晶
を形成させる工程順を示したものであシ、第４′図、第
５′図はそれぞれ第４図、彫５図の中央部縦断面図を示
す。Figure #12 to Figure 5 show the process order of forming a single crystal on the candy film according to the present invention, and Figures 4' and 5' are Figure 4 and Figure 5, respectively. A vertical cross-sectional view of the central part is shown.
先ず半導体基板であるシリコン基板ｌｌ上に、ｖ＠ｔｏ
、の雰囲気、且つ約１０００℃の温度条件による熱酸化
によって約６０００１の厚さの二酸化シリコン［１１２
を形成する（第２図）。First, v@to is placed on a silicon substrate ll, which is a semiconductor substrate.
Silicon dioxide [112
(Figure 2).
次に前述の二酸化シリコン膜１２上にＣＶＤ法（化学気
相成長法）によシ約４ｏｏｏＸの厚みの多結晶シリコン
膜１３を成長させる（餉３図）。Next, a polycrystalline silicon film 13 having a thickness of about 400X is grown on the silicon dioxide film 12 described above by CVD (chemical vapor deposition) (Figure 3).
次に多結晶シリコン膜上にむｙ０２の雰囲気で且つ９０
０℃の温度で熱酸化を行ない約３００〜８００Ｘの厚さ
のマスク用二酸化シリコンａ１６を形成しく館４ＷＪ）
、次に８４図の中央縦断面図が第４′図になるように該
二酸化シリコン１１１６を弗酸系のエツチング振でエッ
チオフし、バターニングを行なう。本発明では該二酸化
シリコン換１６をマスクにしてビームアニールが行なわ
れるようにするものである０
次にｔ４ターン化された二酸化シリコン膜１６と工Ｖチ
オ７によυ施用した多結晶シリコン膜１３の上にキャッ
プ効果を有し且つ光を透過するＣＶＤ二酸二酸化シリコ
ンマ１７５０〜１００Ｘ（２）厚さに成長させ５１５図
）。５′図は館５図の中央部縦断面図である。Next, in an atmosphere of y02 on the polycrystalline silicon film and
Perform thermal oxidation at a temperature of 0°C to form silicon dioxide A16 for a mask with a thickness of approximately 300 to 800X (4WJ)
Next, the silicon dioxide 1116 is etched off using a hydrofluoric acid-based etching solution so that the central vertical cross-sectional view of FIG. 84 becomes that of FIG. 4', and patterning is performed. In the present invention, beam annealing is performed using the silicon dioxide layer 16 as a mask.Next, the silicon dioxide film 16 which has been turned into t4 and the polycrystalline silicon film 13 which has been applied by the process Vthio7 A CVD silicon dioxide polymer having a capping effect and transmitting light is grown to a thickness of 1750-100X (2) on top of the substrate (Figure 515). Figure 5' is a vertical cross-sectional view of the central part of Figure 5.
次に１０〜１４Ｗの強いエネルギーでレーザービームを
該二酸化シリコン膜１７を通して多結晶シリコン［９１
３に照射し、アニールする。このレーザービームの照射
に対し、薄い二酸化シリコン膜１６がマスクの代わりを
果たし、二酸化シリコン膜１６の工Ｖチング端部（第５
′＠中にＡで示す）の下方の多結晶シリコン膜に大きな
温度勾配を与え第５′図中に破線Ｂで示すような亀裂を
誘発させる（従来の欠点を逆に利用したもの）。この亀
裂によシ単結晶形成領域に自由端を形成せしめ従来より
約数倍程度の太き表ｇｒａｌｎサイズの単結晶を成長さ
せることが可能となる。また従来問題であう走差板上の
二酸化シリコン１１１２と多結晶シリコンｌ１１３との
境界面の剥離は前述の第５′図中の３の亀裂に打消され
て発生しない０更に又本発明によれば、光を透過し且つ
キャップ効果を示すＣＶＤ二酸化シリコン膜１３によっ
て形成される単結晶の表面のｔＩｉ形が小さく改善され
る。Next, a laser beam with strong energy of 10 to 14 W is passed through the silicon dioxide film 17 to polycrystalline silicon [91
3 and annealed. The thin silicon dioxide film 16 acts as a mask for this laser beam irradiation, and the etched V-etched end (the fifth
A large temperature gradient is applied to the polycrystalline silicon film below the polycrystalline silicon film (indicated by A in FIG. 5') to induce cracks as indicated by broken lines B in FIG. This crack forms a free end in the single crystal formation region, making it possible to grow a single crystal with a surface gran size that is about several times thicker than the conventional method. Further, the conventional problem of peeling at the interface between silicon dioxide 1112 and polycrystalline silicon 113 on the running plate is canceled out by the cracks 3 in FIG. 5' and does not occur.Furthermore, according to the present invention, The tIi shape of the surface of the single crystal formed by the CVD silicon dioxide film 13 that transmits light and exhibits a capping effect is improved to a small size.
第６図は本発明に係る方法のビームアニールによシ単結
晶化が完了した概略平面図を示すものであシ、前述の如
く本発明は多結晶シリコン膜に亀裂を発生させ、内由端
１９を作る仁とによってより大きなｇｙａｉｓ＞サイズ
の単結晶シリコン２０を形成するのであシ、この際多結
晶シリコンの亀裂部１８には下地の二酸化シリコン膜が
露出した状態となる・
またビームアニールの際ビーム径に比較して（単結晶化
したい領域）の・母ターンが大きい場合はビームのエネ
ルイーグロフィルをコントロールすると共に複数のレー
ザーを使用しても良い。FIG. 6 is a schematic plan view showing completion of single crystallization by beam annealing according to the method according to the present invention. 19 to form a single crystal silicon 20 with a larger gyais>size, and at this time, the underlying silicon dioxide film is exposed in the cracks 18 of the polycrystalline silicon. If the mother turn of the area to be single-crystalized is large compared to the actual beam diameter, it is also possible to control the energy energy of the beam and use multiple lasers.
第１図は従来の単結晶シリコン膜を形成せしめる概略断
面図を示し、第２図ないし館５図は本発明に保る製造方
法を工程順に示した概略断面図であシ、第４′図、館５
′図はそれぞれ給４図、１５図の中央縦断面図を示し、
ｔ＃６図は本発明に係る方法のビームアニールによシ単
結晶化が完了した概略平面図を示す。
１・・・半導体基板、２・・・絶縁膜、３・・・多結晶
シリコン膜、４・・・境界面、４１・・・亀裂部、１１
・・・シリコン基板、１２・・・二酸化シリコン膜、１
３・・・多結晶シリコン膜、１６・・・マスク用二酸化
シリコン膜、１７・・・ＣＶＤ二酸化シリコン膜、１８
・・・亀裂によシ下地二酸化シリコン膜が露出した領域
、１９・・・自由端、２０・・・単結晶シリコン。
手続補正書（方式）
％式％）
１、事件の表示
昭和５６年特許願 第１４５２３５号
２、発明の名称
半導体装置の製造方法
３、補正をする者
事件との関係 特許出願人
名称 （５２２）富士通株式会社
４、代理人
（外 ３ 名）
５、補正命令め日付
昭和５７年１月２６日 （発送日）
６、補正の対象
１）明細書の「発明の詳細な説明」の欄２）明細書の「
図面の簡単な説明」の欄３）図 面 （全図）
７、補正の内容
１）発明の詳細な説明
イ）明細書第４ページ第４行目の［第２図ないしＩＥＳ
図は」を「第２図、第３図、１ＥＡａ図、及び第５ａ図
は」に訂正する。
口）明細書第４ページ第６行目の「第４′図、！１Ｅ５
’図はそれぞれ第４図、第５図の」を「第４ｂ図、第５
ｂ図はそれぞれ第４ａ図、第５ａ図の」に訂正する。
ハ）明細書ｔｉＬ４ページ第１８第１８行管形成しく＠
４図）、次に１１４図の」を１を形成しく第４ａ図）、
次に第４ａ図の」に訂正する。
二）明細書第４ページ第１９行目の「が第４′図に」を
「が＠４ｂ図に」に訂正する。
ホ）明細書ＩＩ５ページＩＩ８行目の「（第５図）。
５′図は第５図の」を「（第５ａ図）。第５ｂ図は第５
島図の」に訂正する。
べ 明細書＄５ページ第１５行目の「（第５′図中ＫＡ
で示す）」を「（ｆＩＩｌ、５ｂ図中ＫＡで示す）」に
訂正する。
ト）明細書第５ページＩ！１７行目の「第５′図中に」
を「第５ｂ図中に」に訂正する。
チ）明細書第６ページ第３行目の「第５′図中の」を「
第５ｂ図中の」に訂正する、
２）図面の簡単な説明
イ）明細書の第７ページ第４行目の［第２図ないし第５
図は］を「第２図、第３図、第４ａ図、及び第５ａ図は
Ｊに訂正する。
口）明細書の１ａ７ペ一ジ！ｓ６行目の［第４′図、る
。
３）図面
図面全図を別紙の通り補正する。
（図番についての補正であり、内容について変更はあり
ません）
８、添付書類の目録
補正図面（ＩＫＩ図、ＩＫ２図、ｗＬ３図、ＩＥ４ａ図
、ＩＥＡｂ図、第５１図、第５ｂ図、第６図） １通回
回
Ｄ 。
＋−ｊＬ１″）
佇 転
匹 因
Ｄ ■Ｕ）
停 佇FIG. 1 shows a schematic cross-sectional view of forming a conventional single-crystal silicon film, and FIGS. , Hall 5
'Figures show central longitudinal cross-sectional views of Figures 4 and 15, respectively.
Figure t#6 shows a schematic plan view of completed single crystallization by beam annealing according to the method of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Polycrystalline silicon film, 4... Boundary surface, 41... Crack part, 11
...Silicon substrate, 12...Silicon dioxide film, 1
3... Polycrystalline silicon film, 16... Silicon dioxide film for mask, 17... CVD silicon dioxide film, 18
. . . Region where the underlying silicon dioxide film is exposed due to cracks, 19 . . . Free end, 20 . . . Single crystal silicon. Procedural amendment (method) % formula %) 1. Indication of the case Patent Application No. 145235 of 1982 2. Name of the invention Method for manufacturing semiconductor devices 3. Person making the amendment Relationship to the case Name of patent applicant (522) Fujitsu Limited 4. Agent (3 others) 5. Date of amendment order January 26, 1980 (shipment date) 6. Subject of amendment 1) "Detailed description of the invention" column 2) of the specification " on the statement
"Brief explanation of the drawings" column 3) Drawings (all drawings) 7. Contents of amendment 1) Detailed explanation of the invention a) [Drawing 2 or IES
``The figures are'' should be corrected to ``Figures 2, 3, 1EAa, and 5a''. Ex) "Figure 4', !1E5" on page 4, line 6 of the specification
``Figures 4 and 5'' are replaced with ``Figures 4b and 5, respectively.''
Figure b has been corrected to ``'' in Figures 4a and 5a, respectively. C) Specification tiL4 page 18 Line 18 tube formation @
Figure 4), then ``114'' to form 1 (Figure 4a),
Next, correct it to `` in Figure 4a. 2) In the 19th line of page 4 of the specification, "is in Figure 4'" is corrected to "is in Figure 4b". E) Change "(Figure 5). Figure 5' is Figure 5" to "(Figure 5a). Figure 5b is Figure 5" on page II, line 8 of Specification II, page 5.
Corrected to "of the island map." ``(KA in Figure 5') on page 5 of the specification, line 15
)" is corrected to "(fIIl, indicated by KA in Figure 5b)". g) Page 5 of the specification I! Line 17: “In Figure 5′”
is corrected to "in Figure 5b". h) In the third line of page 6 of the specification, change “in Figure 5′” to “
2) Brief explanation of the drawings b) [Figures 2 to 5] on page 7, line 4 of the specification
Figure 2, Figure 3, Figure 4a, and Figure 5a are revised to J. ) All drawings are corrected as shown in the attached sheet. (This is an amendment to the drawing number, and there is no change in the content.) 8. Inventory correction drawings of attached documents (IKI drawing, IK2 drawing, wL3 drawing, IE4a drawing, IEAb drawing , Fig. 51, Fig. 5b, Fig. 6) 1 time D .
Claims (1)
に多結晶シリコン展を形成して次に該多結晶シリコン膜
をビームアニールすることによって単結晶シリコン膜を
形成する工程を含む半導体装置の製造方法において； 前記多結晶シリコン膜を形成した彼、該多結晶シリコン
膜上に二酸化シリコン膜を形成し、単結晶形成部に相浩
する該二酸化シリコン展を工Ｖチンダによシ除去し、次
に光を透過し且つキャＶグ効果を有する被覆材を被覆し
た後に前記多結晶シリコン膜をアニールするととを特徴
とする半導体装置の製造方法。[Claims] 1. Form an insulating film on a semiconductor substrate, then form a polycrystalline silicon film on the insulating film, and then beam-anneal the polycrystalline silicon film to form single-crystal silicon. In a method for manufacturing a semiconductor device including a step of forming a film; forming the polycrystalline silicon film, forming a silicon dioxide film on the polycrystalline silicon film, and depositing the silicon dioxide on the single crystal forming portion; 1. A method for manufacturing a semiconductor device, comprising: removing the polycrystalline silicon film using a V-chinder, then covering the polycrystalline silicon film with a coating material that transmits light and has a capacitive effect, and then annealing the polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145235A JPS5846626A (en) | 1981-09-14 | 1981-09-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145235A JPS5846626A (en) | 1981-09-14 | 1981-09-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846626A true JPS5846626A (en) | 1983-03-18 |
| JPH0235450B2 JPH0235450B2 (en) | 1990-08-10 |
Family
ID=15380455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56145235A Granted JPS5846626A (en) | 1981-09-14 | 1981-09-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846626A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61251113A (en) * | 1985-04-30 | 1986-11-08 | Fujitsu Ltd | Single crystallization of non-single crystal layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669837A (en) * | 1979-11-12 | 1981-06-11 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-09-14 JP JP56145235A patent/JPS5846626A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669837A (en) * | 1979-11-12 | 1981-06-11 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61251113A (en) * | 1985-04-30 | 1986-11-08 | Fujitsu Ltd | Single crystallization of non-single crystal layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0235450B2 (en) | 1990-08-10 |
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