JPS5839069A - Semiconductor diaphragm - Google Patents
Semiconductor diaphragmInfo
- Publication number
- JPS5839069A JPS5839069A JP13756281A JP13756281A JPS5839069A JP S5839069 A JPS5839069 A JP S5839069A JP 13756281 A JP13756281 A JP 13756281A JP 13756281 A JP13756281 A JP 13756281A JP S5839069 A JPS5839069 A JP S5839069A
- Authority
- JP
- Japan
- Prior art keywords
- diaphragm
- semiconductor
- thin film
- groove
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 11
- 241000277331 Salmonidae Species 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229920003002 synthetic resin Polymers 0.000 abstract description 3
- 239000000057 synthetic resin Substances 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 230000005496 eutectics Effects 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 230000007613 environmental effect Effects 0.000 abstract 1
- 239000002585 base Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000866 electrolytic etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
Abstract
Description
【発明の詳細な説明】
この発ｗＡは圧力鳴差圧・絶対圧など音測定する機器に
おいて検出素子として使用される半導体ダイヤフラムの
改良に関する。 半導体ダイヤフラム上にピエゾ抵抗素
子を形成したものを検出素子として用いる圧力Ｓ差圧・
絶対圧などの測定器は今年多見京れゐものであるが、そ
の性能違威上殊ＶｃｌＩＡ点とされるの肱、ピエゾ抵抗
係数の温度変化に起因する測定スパンの温度変化、周囲
温度変化によって半導体ダイヤ７５五に加わる歪応力に
起因するゼロ点の温度ドリフトなどである。 本発明は
、上記のゼロ点の温度ドリフトの改良にかかるもので、
半導体ダイヤプラムとそれが取り付けられる取付台及び
覗り付けのための接合層などとの熱膨張係数の差によっ
て薄膜ダイヤフラムに加わる熱歪の影譬を減少すること
を目的とする。DETAILED DESCRIPTION OF THE INVENTION This invention relates to an improvement of a semiconductor diaphragm used as a detection element in a device for measuring sound such as differential pressure or absolute pressure. Pressure S differential pressure using a piezoresistive element formed on a semiconductor diaphragm as a detection element
Absolute pressure and other measuring instruments have been introduced this year, but their performance is particularly high due to temperature changes at the VclIA point, temperature changes in the measurement span due to temperature changes in the piezoresistance coefficient, and ambient temperature changes. This includes temperature drift at the zero point due to strain stress applied to the semiconductor diamond 755 due to the stress. The present invention relates to improving the temperature drift of the above-mentioned zero point,
The object of the present invention is to reduce the influence of thermal strain applied to a thin film diaphragm due to the difference in thermal expansion coefficient between a semiconductor diaphragm, a mounting base to which it is attached, a bonding layer for viewing, and the like.
上記目的を達成するための従来の提案として、特開１８
５４−９９５８５号公報に開示の１のがある。As a conventional proposal to achieve the above purpose, JP-A-18
No. 54-99585 discloses one.
これば圧力・差圧°・絶対圧計なとの受圧部を構成する
部材から検出素子である半導体ダイヤフラムに加わる歪
応力を減らすために特殊な構造を採用した取付台管用し
るものであるが、その取付台の構造が複雑なため製造上
難点があると共に、歪応力の伝達を完全にはなくしえな
いなどの欠点がある。 また他の従来の提案として、実
開昭５４−１４３２７５号公報に開示のものが１１）、
これは半導体ダイヤ７２ふと同じ素材からなる取付台を
用いることによシ、取付台と半導体ダイヤフラムの熱膨
張係数の差による熱歪応力の発生を防止することを目的
とし、取付台に溝を形設することによシ、この目的をよ
り完全に達成しようとするものである。 しかし、上記
いずれの提案のものも半導体ダイヤフラム自身は何ら歪
を吸収する手段を有しておらず、半導体ダイヤ７５ムと
取付台を一体化するためｆ′％接合層が起歪部として発
生する歪応力を吸収することばてきないという難点があ
る。This is a type of mounting pipe that has a special structure to reduce the strain stress applied to the semiconductor diaphragm, which is the detection element, from the members that make up the pressure receiving part such as pressure, differential pressure, and absolute pressure gauges. The structure of the mounting base is complicated, which makes it difficult to manufacture, and it also has drawbacks such as the fact that the transmission of strain stress cannot be completely eliminated. Other conventional proposals include those disclosed in Japanese Utility Model Application Publication No. 54-14327511),
This is done by using a mounting base made of the same material as the semiconductor diaphragm, and with the aim of preventing the generation of thermal strain stress due to the difference in thermal expansion coefficient between the mounting base and the semiconductor diaphragm, grooves are formed in the mounting base. By establishing this, we aim to more fully achieve this objective. However, in any of the above proposals, the semiconductor diaphragm itself does not have any means to absorb strain, and in order to integrate the semiconductor diaphragm and the mounting base, the f'% bonding layer is generated as a strain-generating part. The problem is that there is no language that can absorb strain stress.
半導体ダイヤフラムと取付台會一体化するための方法と
してμ、合成樹脂による接着、低一点ガラスによる接合
、金−シリコンの共晶合金による接合、陽Ｉｉ＊合法、
金属ソルダ一層による接合など種々の方法が既に提案・
実用化されているが、上記いずれの方法を用いても、接
合層には接合時に発生した歪応力が残ると共に、半導体
ダイヤスラムと接合層中取付台の熱膨張係数を完全には
一致させることはできなめために熱歪応力が薄膜ダイヤ
フラムに加わることはまぬがれ得ない。Methods for integrating the semiconductor diaphragm and the mounting table include μ, synthetic resin bonding, low single point glass bonding, gold-silicon eutectic alloy bonding, positive Ii* method,
Various methods such as bonding using a single layer of metal solder have already been proposed and
Although these methods have been put to practical use, no matter which method is used, the strain stress generated during bonding remains in the bonding layer, and the thermal expansion coefficients of the semiconductor diaphragm and the mount in the bonding layer cannot be completely matched. Because of the slanted surface, it is inevitable that thermal strain stress will be applied to the thin film diaphragm.
この発ＢＡは、との悪影響をと９除き、周囲温度変化に
対して安定に動作する。 すなわち熱歪応力が薄膜ダイ
ヤフラムに加わることの無い半導体ダイヤフラムを提供
するものであり、圧力・差圧・絶対圧計等に好適に使用
される。This BA operates stably against changes in ambient temperature, excluding the adverse effects of . In other words, the present invention provides a semiconductor diaphragm in which thermal strain stress is not applied to the thin film diaphragm, and is suitably used in pressure, differential pressure, absolute pressure gauges, and the like.
すなわち、この発明の半導体ダイヤフラムは、半導体単
結晶の板状チップの下面中央部を上面へ向けて凹ませて
中央部を薄肉にしてその中央部を薄膜ダイヤフラムとす
ると共に、その周囲の比較的厚内の部分を周辺固定部と
し％―らにその周辺固定部に前記薄膜ダイヤフラムを取
り囲むように応力吸収の為の細く深い＊１形成して構成
さｆまたものである。 こめ半導体ダイヤプラムμ、取
付台から接合層を介しであるいは接合層自体から半導体
ダイヤフラムの周辺固定部に加わる歪応力が薄膜ダイヤ
フラムへと伝わるのを、細く深い溝を設けることにより
防止することができるので、半導体ダイヤフラムとの熱
膨張係数の一致、歪応力の伝達防止などを考慮し九特別
な取付台を必要とせず、半導体ダイヤフラムと取付台の
！！合の手法も容易で広い温度範囲にわ大って安定に動
作しりろものである。That is, in the semiconductor diaphragm of the present invention, the central part of the lower surface of a semiconductor single crystal plate chip is concave toward the upper surface to make the central part thinner, and the central part becomes a thin film diaphragm. The inner part is used as a peripheral fixing part, and the peripheral fixing part is formed thin and deep *1 for stress absorption so as to surround the thin film diaphragm. By providing a narrow and deep groove in the semiconductor diaphragm μ, it is possible to prevent the strain stress applied to the peripheral fixing portion of the semiconductor diaphragm from being transmitted from the mounting base through the bonding layer or from the bonding layer itself to the thin film diaphragm. Therefore, in consideration of matching the coefficient of thermal expansion with the semiconductor diaphragm and preventing transmission of strain stress, etc., there is no need for a special mounting base, and the mounting base can be attached to the semiconductor diaphragm! ! This method is also simple and operates stably over a wide temperature range.
以下、図に示す実施例に基いて、この発明を詳説する。Hereinafter, this invention will be explained in detail based on embodiments shown in the drawings.
１８１図に示す（１）ｕ、この発明の半導体ダイヤフラ
ムの一実施例であるシリコンダイヤスラムである。(1) u shown in Fig. 181 is a silicon diaphragm which is an embodiment of the semiconductor diaphragm of the present invention.
このシリコンダイヤフラム（１３は、（ｔｌＯ）面を有
するシリコン単結晶で概略７ｓｗＸ７ｓｗＸ２００μｍ
の正方形の板状チップの下面中央部（２）を電解エツチ
ング等により削除して、その中央部に厚さ十数声調の薄
膜ダイヤフラムβ）を円形に形成したものである。 円
形の直径はｚ−３ｍである。This silicon diaphragm (13 is a silicon single crystal with a (tlO) plane and has an approximate size of 7 sw x 7 sw x 200 μm.
The center part (2) of the lower surface of the square plate-shaped chip is removed by electrolytic etching or the like, and a circular thin film diaphragm β) having a thickness of about ten tones is formed in the center part. The diameter of the circle is z-3m.
薄膜ダイヤスラム（３１ｆ１周囲の厚さ２００声肩 の
部分は周辺固定５（４）である。Thin film diaphragm (200mm thickness around 31f1) The shoulder part is peripherally fixed 5 (4).
薄膜ダイヤフラム（３１ｔ−取９ｓむように周辺固定部
（４）に形設されえＩＩＩＩは歪応力吸収のための細く
深い溝（６）であ夛、周辺固定部（４）の下面（５）
′に開口しており、それら開口（６ｍ）（６ｂ）（６ｅ
）（＠ｄ） ｕ四辺形をなしている。 そしてその四辺
形の辺をなす開口の長手方向はいずれ４（ｘｉｚ）軸方
向を向いている。 開口の幅は数声講から数＋ｐｍで、
溝の深さは周辺固定部（４）の厚みの概略８０〜９ｏチ
すなわち約１６０−ＩＪＩＯ声肩である。A thin film diaphragm (31t-9s) is formed on the peripheral fixing part (4).
', and these openings (6m) (6b) (6e
) (@d) It forms a u quadrilateral. The longitudinal direction of the opening forming the sides of the quadrilateral is always oriented in the 4 (xiz) axis direction. The width of the aperture is from a few notes to a few + pm,
The depth of the groove is approximately 80 to 9 degrees of the thickness of the peripheral fixing portion (4), that is, approximately 160 degrees.
このような歪応力吸収の為の溝（６）ハ、周辺固定部（
４）の下面（５）［５ｉ０１．５ｌｊＮ４などの薄膜を
形成し大径上記開口（６ａ）（６ｂ）（６ｅ）（６ｄ）
Ｋ対応した四辺形パターンをフォト・リソグラフィー
の技術によりくり抜いたのち、Ａ ＰＷ （Ａｍ１ｎ＠
ｐｙｏｃａ−ｔｅｃｈｏｌ Ｗａｔｅｒ）エツチングを
施すことで極めて好適に形設できる。 すなわち、ＡＰ
Ｗエツチングによれば（１１１）面はほとんどエツチン
グされない。 従って、（１１０）面上に＜１１２＞軸
方向に長手方向を有するように開けられたエッチジグ窓
を有するシリコンをＡＰＷエツチングすれば、深ζ方向
にのみエツチングされ、横方向のエツチングすなわちア
ンダーエッチ１ｊｔｘｔｘ）面があられれるのでほとん
ど進まない。 結局、下面（５）が上記四辺形パターン
の深さ方向にのみエツチングされて下面（５） Ｋ垂直
な＃１８ （７ｍ）（７ｂ）（７ｃ）（７ｄ）をもつ歪
一応力吸収の為の溝（６）が狭く深い断面略Ｕ字状に
形 。Groove (6) C for absorbing such strain stress, peripheral fixing part (
4) Lower surface (5) Form a thin film such as [5i01.5ljN4 and open the above large diameter openings (6a) (6b) (6e) (6d)
After cutting out a quadrilateral pattern corresponding to K using photolithography technology, A PW (Am1n@
It can be formed very suitably by etching (pyoca-techol water). That is, AP
According to W etching, the (111) plane is hardly etched. Therefore, if APW etching is performed on silicon having an etch jig window opened on the (110) plane so that the longitudinal direction is in the <112> axis direction, the etching will be performed only in the deep ζ direction, and the etching will occur in the lateral direction, that is, underetch 1jtxtx. ) The surface is so rough that little progress is made. As a result, the lower surface (5) is etched only in the depth direction of the quadrilateral pattern, and the lower surface (5) has K perpendicular #18 (7m) (7b) (7c) (7d) for stress absorption. The groove (6) is narrow and deep, with a roughly U-shaped cross section.
成されることになるからである。 歪応力吸収の為の溝
（６）の深シμエツチング時間によシコントロールで匙
、幅は前記フォト・リソグラフィー技術によってエツチ
ングマスクに開けられる四辺形パターンの辺の＠によっ
てコントロールできる。Because it will be done. The depth of the groove (6) for absorbing strain stress can be controlled by the etching time, and the width can be controlled by the sides of the quadrilateral pattern formed in the etching mask by the photolithography technique.
このようにして周辺固定５（４）の下面（５） Ｋ開口
する断面略Ｕ字状の歪応力吸収の為のｆｌｉ ［６１を
形成されたシリコンダイヤフラム（１）汀、纂４図に示
すように、その上１ｉｉＫ７オト・リソグラフィーの手
法に工ｐたとえばピエゾ抵抗素チーより成る歪ゲージ１
ＬＩ１９１ｔ−形成され、歪応力吸収の為の溝（６）よ
り外側の周辺同定部下面（５）ｆ＞取付面（５ａ）の部
分で取付台−に取り付けられ、圧力・差圧・絶対圧尋の
検出素子■とされる。In this way, the lower surface (5) of the peripheral fixing 5 (4) is formed with a silicon diaphragm (1) having an approximately U-shaped cross section with an opening for strain stress absorption (1), as shown in Figure 4. In addition, for example, a strain gauge 1 made of a piezoresistive element may be applied to the photolithography method.
LI191t is formed, and is attached to the mounting base at the area where the peripheral identification lower surface (5) f > mounting surface (5a) outside the groove (6) for strain stress absorption, and pressure, differential pressure, and absolute pressure. It is considered as the detection element (■).
上記シリコンダイヤフラム（υでは、上記説明のように
それ自身が歪応力吸収の為の＄ １６１ ｆｔ有してい
るから、周辺固定＠（４）から薄膜ダイヤフラムａ）へ
の歪応力の伝達がほとんどない。 従って、歪応力によ
る零点の温度ドｖ７トが非常に少く、極めて安定に動作
しうる％ｔｌである。 また、取付台頭を特殊な構造と
する必要もなく、素材もガラス、シリコン、アル建す、
金属などの素材を任意に使用することができる。 さら
にその上、取付台頭への取り付けを、低融点ガラス、合
成樹脂接着剤、金−シリコンの共晶を利用する方法など
任意に選択して行うことができる。 また歪応力吸収の
為の連出）が狭く深い断面Ｕ字状であるから、ダイヤフ
ラム（１）の両面の差圧によりブリッジ部υに生ずる応
力に剪断応力になるが、シリコンセ剪断応力に対して強
いので、大きな差圧下でも強度的に問題なく使用できる
。Since the silicon diaphragm (υ) itself has $161 ft for absorbing strain and stress as explained above, there is almost no transmission of strain and stress from the peripheral fixation @(4) to the thin film diaphragm a). . Therefore, the temperature dot v7 at the zero point due to strain stress is very small, and the temperature is %tl, which allows extremely stable operation. In addition, there is no need for a special structure for the mounting base, and materials such as glass, silicone, aluminum, etc.
Any material such as metal can be used. Furthermore, attachment to the mounting base can be carried out by any method such as using low melting point glass, synthetic resin adhesive, or gold-silicon eutectic. In addition, since the diaphragm (1) has a narrow and deep U-shaped cross section, the stress generated in the bridge portion υ due to the differential pressure on both sides of the diaphragm (1) becomes shear stress, but the silicon shear stress Because it is strong, it can be used even under large differential pressure without any problems in terms of strength.
他の実施例とし゛ては、歪応力吸収の為の溝をダイヤフ
ラムの上面に開口する溝とするもの、あるいは下面に開
口する溝と上面に開口する溝との二重の溝とするものが
挙げられる。 また、他の異方向性エツチングたとえば
アルカリエツチングを用いて歪応力吸収の為の溝を形成
してもよい。Other examples include one in which the groove for absorbing strain stress is a groove that opens on the top surface of the diaphragm, or one in which the groove is a double groove with a groove that opens on the bottom surface and a groove that opens on the top surface. It will be done. Further, grooves for absorbing strain stress may be formed using other anisotropic etching such as alkali etching.
さらにスパッタリング、プラズマエツチング、電子ビー
ム加工などを用いて歪応力吸収の為の溝を形成してもよ
い、 この場合には、（１１２）軸方向の辺をもつ四辺
形パターンの溝とする必要がないから、円形パターンな
どの任意のバター／の溝を形設することができる。 ま
たさらに、半導体をゲルマニウムとしたものが挙けられ
る。Furthermore, grooves for absorbing strain stress may be formed using sputtering, plasma etching, electron beam machining, etc. In this case, it is necessary to form grooves in a quadrilateral pattern with sides in the (112) axis direction. Since there is no pattern, any butter/grooves can be formed, such as a circular pattern. Furthermore, examples include those using germanium as the semiconductor.
８８１図はこの発明Ｖ半導体ダイヤフラムの一実施例の
ｌＩ２図におけるＩ−Ｉ噺面図、第２図ＩＷｌ１図に示
す半導体ダイヤフラムの底面図、ｉｉＪ図ｔｉｔ同じく
底面部を見た斜視図、ｌＩ４図は第１図に示す半導体ダ
イヤフラムを用いえ圧力検出素子の縦端面図である。
（１３・−・シリコンダイヤフラム、■・・・薄膜ダイ
ヤスラム、（４）・・・周辺■定部、（６）−下面、（
５Ｂ）・・・取付面、（６１・・・歪応力吸収の為の溝
、（６ｍ）（６ｂ）（６ｅ）（６ｄ） ・ｉ１口、（７
ｍ）（７ｂ）（７ｃ）（７ｄ） −溝壁、（９）・・・
ピエゾ抵抗素子、−・・・取付台、（ｌｌ−・・圧力検
出素子。
特許出願人 株式会社島津製作所Figure 881 is an I-I side view in Figure 1I2 of an embodiment of the semiconductor diaphragm of this invention V, Figure 2 is a bottom view of the semiconductor diaphragm shown in Figure 11, Figure iiJ is a perspective view of the same bottom view, and Figure 1I4. 2 is a longitudinal end view of a pressure sensing element using the semiconductor diaphragm shown in FIG. 1. FIG. (13--Silicon diaphragm, ■--Thin film diaphragm, (4)--Periphery ■ Fixed part, (6)--Bottom surface, (
5B)...Mounting surface, (61...Groove for strain stress absorption, (6m) (6b) (6e) (6d) ・i1 port, (7
m) (7b) (7c) (7d) - Groove wall, (9)...
Piezoresistance element, -...Mounting base, (ll-...Pressure detection element. Patent applicant: Shimadzu Corporation
Claims (1)
けて凹ませて薄膜ダイヤフラムを形成すると共に、その
周囲の比較的厚内の部分を周辺固定部とした半導体ダイ
ヤフラムにおいて、−薄膜ダイヤフラムを取り囲むよう
に周辺固定ｉＢＫ細く深い鱒を形成したことを特徴とす
る半導体ダイヤフラム。 １ 半導体がシリコンであり、板状チップの上・下面を
（口０）ｍとし、下面（１ｔｏ）面上で（１１り軸方向
に辺をもつ４辺形の各辺に沿って異方向性エツチングを
施して、周辺固定部下面に開口する細く深い溝を形成し
てなる請求の範囲第五項記載の半導体ダイヤフラム。 １ 歪吸収溝よｐ外側の周辺固定部下面が′、半導体ダ
イヤフラム教付台への取付面となる請求の範ｆｌｌ１１
項記載の半導体ダイヤフラム。 表 異方向性エツチングが、Ａ Ｐ Ｗ （Ａｍｉ ｎ
＠Ｐ）’ −ｒｏｅａｔｅｅｈｏｌ Ｗａｔ＠ｒ）エツ
チングである請求の範囲８２項記載の半導体ダイヤフラ
ム。 ５、ダイヤフラム上面にピエゾ抵抗素子が形成されてな
る請求の範１ｉ１Ｅ１項から謳４項のいずれかに記載の
半導体ダイヤフラム、。[Scope of Claims] 1. A semiconductor in which the central part of the lower surface of a semiconductor single-crystal plate-like chip is recessed toward the upper surface to form a thin film diaphragm, and a relatively thick part around the thin film diaphragm is used as a peripheral fixing part. A semiconductor diaphragm characterized in that - a periphery fixed iBK thin and deep trout is formed in a diaphragm so as to surround a thin film diaphragm. 1 The semiconductor is silicon. The semiconductor diaphragm according to claim 5, wherein the semiconductor diaphragm is formed by etching to form a narrow and deep groove opening on the lower surface of the peripheral fixing member. Scope of claim that is the mounting surface to the standFll11
Semiconductor diaphragm described in Section 1. Table Anisotropic etching is A P W (Amin
83. The semiconductor diaphragm according to claim 82, wherein the semiconductor diaphragm is etched. 5. The semiconductor diaphragm according to any one of claims 1i1E1 to 4, wherein a piezoresistive element is formed on the upper surface of the diaphragm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13756281A JPS5839069A (en) | 1981-08-31 | 1981-08-31 | Semiconductor diaphragm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13756281A JPS5839069A (en) | 1981-08-31 | 1981-08-31 | Semiconductor diaphragm |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5839069A true JPS5839069A (en) | 1983-03-07 |
| JPH0158673B2 JPH0158673B2 (en) | 1989-12-13 |
Family
ID=15201618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13756281A Granted JPS5839069A (en) | 1981-08-31 | 1981-08-31 | Semiconductor diaphragm |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839069A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60183156A (en) * | 1984-03-01 | 1985-09-18 | Canon Inc | Ink jet recording head |
| JPS6198552A (en) * | 1984-10-19 | 1986-05-16 | Canon Inc | Manufacture of liquid jet recording head |
| JPS63283073A (en) * | 1987-05-15 | 1988-11-18 | Toshiba Corp | Semiconductor pressure sensor |
| JPH01127268U (en) * | 1988-02-23 | 1989-08-31 | ||
| JPH0363834U (en) * | 1989-10-24 | 1991-06-21 | ||
| WO2000029822A1 (en) * | 1998-11-12 | 2000-05-25 | Maxim Integrated Products, Inc. | Chip-scale packaged pressure sensor |
| WO2000029823A1 (en) * | 1998-11-12 | 2000-05-25 | Maxim Integrated Products, Inc. | Hermetic packaging for semiconductor pressure sensors |
| WO2004055569A1 (en) * | 2002-12-17 | 2004-07-01 | Sharan Instruments Corporation | Optical element fixing structure, optical element fixing body, optical element, and optical element holder |
| JP2013178182A (en) * | 2012-02-29 | 2013-09-09 | Alps Electric Co Ltd | Capacitive physical quantity sensor and manufacturing method thereof |
| JP2013178181A (en) * | 2012-02-29 | 2013-09-09 | Alps Electric Co Ltd | Capacitive physical quantity sensor and manufacturing method thereof |
-
1981
- 1981-08-31 JP JP13756281A patent/JPS5839069A/en active Granted
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60183156A (en) * | 1984-03-01 | 1985-09-18 | Canon Inc | Ink jet recording head |
| JPS6198552A (en) * | 1984-10-19 | 1986-05-16 | Canon Inc | Manufacture of liquid jet recording head |
| JPS63283073A (en) * | 1987-05-15 | 1988-11-18 | Toshiba Corp | Semiconductor pressure sensor |
| JPH01127268U (en) * | 1988-02-23 | 1989-08-31 | ||
| JPH0363834U (en) * | 1989-10-24 | 1991-06-21 | ||
| WO2000029822A1 (en) * | 1998-11-12 | 2000-05-25 | Maxim Integrated Products, Inc. | Chip-scale packaged pressure sensor |
| WO2000029823A1 (en) * | 1998-11-12 | 2000-05-25 | Maxim Integrated Products, Inc. | Hermetic packaging for semiconductor pressure sensors |
| US6346742B1 (en) | 1998-11-12 | 2002-02-12 | Maxim Integrated Products, Inc. | Chip-scale packaged pressure sensor |
| US6351996B1 (en) | 1998-11-12 | 2002-03-05 | Maxim Integrated Products, Inc. | Hermetic packaging for semiconductor pressure sensors |
| WO2004055569A1 (en) * | 2002-12-17 | 2004-07-01 | Sharan Instruments Corporation | Optical element fixing structure, optical element fixing body, optical element, and optical element holder |
| US7692883B2 (en) | 2002-12-17 | 2010-04-06 | Sharan Instruments Corporation | Optical element fixing structure, optical element fixing body, optical element, and optical element holder |
| JP2013178182A (en) * | 2012-02-29 | 2013-09-09 | Alps Electric Co Ltd | Capacitive physical quantity sensor and manufacturing method thereof |
| JP2013178181A (en) * | 2012-02-29 | 2013-09-09 | Alps Electric Co Ltd | Capacitive physical quantity sensor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0158673B2 (en) | 1989-12-13 |
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