JPS5827223A - Direct memory access system - Google Patents

Abstract

PURPOSE:To enable a processor to freely access to a DMA memory even during DMA period by providing plural DMA memories and changing the connection route accessing to them alternately. CONSTITUTION:Plural, for instance two, DMA memories 6A, 6B to which the same address is allotted looked from a CPU are provided. A DMA controller 7 changes and controls changeover circuits S1, S2 so as to make the CPU access to other memory when a DMA controller 7 has accessed to one memory 6B, so as to make the CPU access to one memory 6B when the controller 7 has accessed to other memory 6A. By this way, the CPU can freely access to the DMA memory even during DMA period, and can perform DMA memory access and data processing simultaneously with DMA transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides direct memory access (hereinafter referred to as DMA).
This is related to the improvement of the method (sometimes written as

DM independent from the processor (CPU) on the input/output device side
A controller is provided, and a dedicated data transfer path is provided between the input/output device including the controller and the DMA memory, and the Kf-Y is transferred to the DMA under the control of the controller in accordance with a command given from the CPU. This transfer period (hereinafter referred to as DMA period) for direct transfer to memory,
A DMA method is already well known in which the controller notifies the program by issuing a CPUK interrupt when the period ends, and thereafter the CPU can access the DMA memory. In such a DMA system, since the CPU cannot access the DMA memory during the DMA period, the CPU
There is a problem that processing at U is delayed.

FIG. 1 is a block diagram showing a conventional DMA system. In the figure, 1 is a microprocessor, 2 is a read-only memory (ROM) that stores programs, 3 is a random access memory (RAM) that stores data, 4 is an input/output device (I10 device), 5 is a bus gate, 6 is DMA memory, 7 is DMA controller (to be precise, DM
8 indicates a data transfer path, and 9 indicates a CPU bus.

In FIG. 1, a DMA controller 7 directly transfers data to a DMA memory 6 via a transfer path 8.
During this period, bus gate 5 is open and buses 9 to D
The MA memory 6 is disconnected and the microprocessor 1 is connected to the DM
A memory 6 cannot be accessed. During this period, the microprocessor 1 uses the ROM 2 and RAM 3 via the bus 9.
, i/.

The processing operation continues while accessing the device 4. In this way, during the DMA period, the microprocessor 1
The fact that the A memory 6 cannot be accessed means that the work in the processor 1, which cannot be processed unless the data stored in the DMA memory 6 is brought in, is delayed by the DMA period.

In particular, in processing systems that process image data, when using an industrial television camera as an image input sensor, image data is transferred in DMA for one screen time (16.7 ms).
After the microprocessor captures image data into the DMA memory, it performs data processing based on the captured data. By the time the timing to capture image data in DMA mode arrives, the processor's access to the DMA memory must be completed. This is a problem because image data generally has a large amount of data and the time required to process it also increases. Furthermore, in order to increase data processing efficiency in the processor, it is necessary to shorten the image data acquisition cycle as much as possible. In achieving the processing efficiency required of processors, there are limitations in conventional DMA methods, namely, the inability of processors to freely access DMA memory;
can be a fatal flaw.

The present invention has been made to solve the problems in the prior art as described above, and therefore, the purpose of the present invention is to:
An object of the present invention is to provide a DMA system that allows a processor to freely access a DMA memory even during a DMA period.

The main point of the configuration of the present invention is that a plurality of DMA memories with the same address assignment are prepared, and when the DMA controller is accessing one memory, the processor can access the other memory. The processor is configured to alternately switch the connection path for accessing the memory so that the processor can access one memory while accessing the other memory.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, 6A and 6B are DMA memories, 7 is a DMA controller, 9 is a CPU bus, 10 is a switching signal line, 11 is a DMA bus, 814 is a CPU bus switching circuit,
S2 is a DMA bus switching circuit.

Now, in FIG. 2, the CPU bus switching circuit S1
This is a gate circuit for switching and connecting the U bus 9 (including the 7' bus, address bus, and control bus) between the DMA memories 6A and 6B. DMA memory 6A
, 6B are assigned the same address from the CPU's perspective. The DMA bus switching circuit S2 is a gate circuit for switching and connecting the DMA bus 11 (including f-tabus and control bus) from the DMA controller 7 between the DMA memories 6A and 6B. DMA controller 7
transfers data via the DMA bus 11 to the DMA memory 6A.
Alternatively, at the same time as writing to 6B, a switching signal is sent to the switching circuits 81 and 82 via the signal line 10.

The DMA memory 6A is connected to the CP via the b contact of the switching circuit S1.
When connected to U/(S 9, cough memory 6A is connected to D
It is separated from the MA bus 11. At this time, the DMA memory 6B is connected to the DMA bus 1 via the contact of the switching circuit S2.
1 and is separated from the CPU bus 9. Depending on whether the level of the switching signal output from the controller 7 onto the switching signal line 10 is high or low, the switching circuit Sl,
The contact switching at 82 can be performed to reverse the connection relationship described above.

With the above circuit configuration, for example, during the period when the CPU is accessing the DMA memory 6A, the DMA memory 6B
It becomes possible to transfer data from the controller 7 in DMA mode. In this embodiment, at the same time as the DMA data transfer from the controller 7 is completed, the polarity level of the switching signal outputted from the DMA controller 7 onto the signal line 10 is changed, so that the DM immediately after receiving the DMA data transfer is
A memory is connected to the CPU bus 9 and is designed to be accessible from the CPU. Regarding the software, by configuring a new MA data processing program to be started at this timing, it will continue to process data from the other DM during the next DMA period.
A memory can be accessed.

As explained above, according to the present invention, 2
By preparing two sets of DMA memories, one DM
Even while the A memory is coupled to the CPU, DMA data transfer to the other DMA memory is possible. Therefore C
The PU constantly switches between two sets of DMA memories.
It becomes possible to access the MA memory.

In addition, since each DMA memory has exactly the same address assignment, there is no need to consider which DMA memory to access from the software side of the CPU, so there is no increase in software burden. There is an advantage.

As explained above, this invention also provides DM during the DMA period.
This method was devised to extend the DMA memory access time so that the A memory access time extends, but if you think about it conversely, it can also be applied to extend the DMA period. For example, when capturing images using a linear sensor, it may be necessary to start capturing the next image immediately after capturing all images. The present invention can also be applied to such devices to perform DMA memory access and data processing simultaneously with DMA data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional DMA system, and FIG. 2 is a block diagram showing an embodiment of the present invention. Code explanation 1... Microprocessor, 2... ROM, 3...
・RAM, 4... i10 device, 5... bus gate, 6... DMA memory, 7... DMA controller, 8... data transfer path, 9... CPU bus, 10
...Switching signal line, 11...DMA bus agent Patent attorney Akio Namiki Patent attorney Kiyoshi Matsuzaki Figure 1 Figure 2

Claims (1)

[Claims] 1) Direct memory access (hereinafter abbreviated as DMA) In a DMA system that has MA memory that can be accessed independently from the controller and processor, multiple DMA memories with the same address assignment are provided, and the controller accesses one memory. A connection path for accessing memory such that when the controller is accessing the other memory, the processor can access the other memory, and when the controller is accessing the other memory, the processor can access the other memory. A direct memory access method characterized by switching alternately.