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JPS5825968A - Overlapping dot printer - Google Patents

Overlapping dot printer

Info

Publication number
JPS5825968A
JPS5825968A JP56123587A JP12358781A JPS5825968A JP S5825968 A JPS5825968 A JP S5825968A JP 56123587 A JP56123587 A JP 56123587A JP 12358781 A JP12358781 A JP 12358781A JP S5825968 A JPS5825968 A JP S5825968A
Authority
JP
Japan
Prior art keywords
gate
interpolation
dots
input
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56123587A
Other languages
Japanese (ja)
Other versions
JPH0216219B2 (en
Inventor
Hiroshi Sakai
洋 酒井
Masami Ujiie
氏家 正美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56123587A priority Critical patent/JPS5825968A/en
Publication of JPS5825968A publication Critical patent/JPS5825968A/en
Publication of JPH0216219B2 publication Critical patent/JPH0216219B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00Geometric image transformations in the plane of the image
    • G06T3/40Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4007Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Image Processing (AREA)
  • Fax Reproducing Arrangements (AREA)

Abstract

PURPOSE:To obtain characters having high quality by means of a simple head by mounting a circuit, which does not conduct overlapping to characters of which the concentration of dot density of an original pattern is remarkable, to a dot printer which uses the original pattern as an investigating point and inserts dots around the point as interpolation points. CONSTITUTION:Arithmetic operation ABCD is executed because A, B, C, D are inputted to the input of an AND gate G1, and interpolation not conducted because 1 is outputted from an OR gate G9 when the result is 1. Arithmetic operation A'B'C'D' is executed because A', B', C', D' are inputted to an AND gate G2, and the result is added to one of the input of an AND gate G8. In inhibit gates G3-G6, on the other hand, the arithmetic operation of ACD, ABD, ABC and BCD is executed to each, and the result is added to the other of the input of the AND gate G8 through an OR gate G7 when even only one among them is 1. Consequently, 1 is outputted from the AND gate G8, and outputted from the OR gate G9. Accordingly, interpolation is not conducted.

Description

【発明の詳細な説明】 この発明は、高精細で文字品質の喪い印字が得られるよ
うにした重複ドツト印字装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an overlapping dot printing device capable of producing high-definition, low quality printing.

従来、ドツトプリンタの印字品質を向上するためKは印
刷ヘッドのワイヤ数を多クシ、かつワイヤ径を小さくす
る必要があり、@格および寿命に問題があった。そこで
、ワイヤ数の少ない簡易な印刷ヘッドを用い【高品質な
文字を得るための手段として重複ドツト印字方式が検討
されている。
Conventionally, in order to improve the printing quality of dot printers, it was necessary to increase the number of wires in the print head and reduce the diameter of the wires, which caused problems in quality and service life. Therefore, an overlapping dot printing method is being considered as a means to obtain high-quality characters using a simple print head with a small number of wires.

第tS<より重複ドラF印字の原理を簡単に説明する。The principle of overlapping drum F printing will be briefly explained from tS<.

この図でO印は1文字の原パターンを示す、この原パタ
ーンを探索点として上下、左右および斜め方向のamす
るドラFとの間に、0印で示すドツトを補間点とし【挿
入する。このような手at、原パターンのすべてのドツ
トに対して施すことにより、文字の高品質化が期待でき
る。しかし、このような手法は1画数が大きく複雑な構
成の文字の場合、文字品質の劣化を招くことがある。
In this figure, the O mark indicates the original pattern of one character.Using this original pattern as a search point, dots indicated by the 0 mark are inserted as interpolation points between the dots F that move upward, downward, left, right, and diagonally. By applying this to all dots of the original pattern, it is expected that the quality of the characters will be improved. However, in the case of characters having a large number of strokes and a complicated structure, such a method may lead to deterioration of character quality.

第2図(a)〜(d)は重複した場合と、しない場合と
の比較を示したものである。(1)は重複しない場合、
(b)は重複した場合であり、(e)、(d)はそれぞ
れ(a)、(b) Icよってインクのにじみがある場
合である。(41)&C示すように原パターンのドツト
書度が高い部分では、白色部がほとんどつぶれているこ
とがわかる。
FIGS. 2(a) to 2(d) show a comparison between a case where there is overlap and a case where there is no overlap. If (1) does not overlap,
(b) is a case where there is overlap, and (e) and (d) are cases where there is ink bleeding due to (a) and (b) Ic, respectively. (41) As shown in &C, it can be seen that in the portion of the original pattern where the dot writing quality is high, the white portion is almost crushed.

この発明は1以上のような火点な解決するため。This invention aims to solve one or more such flash points.

1KAI−ンのドツト密度集中が著しい文字につい【は
重複を実行しない機能を施したものである。
Characters with significant concentration of dots in 1 KAI-tone are provided with a function to prevent duplication.

以下、この発明の詳細な説明する。The present invention will be explained in detail below.

第3図〜第S図は、文字の原パターンのドツト集中によ
る文字の1つぶれ”を生じる原因となるキーパターンの
例を示したものである。第3図において・Cは、原パタ
ーン(斜線i施したQ印)の補集合の任意の格子点を示
す、第3図は格子点Cを中心k、上下、左右のドッシの
数n(斜線を施したもの)が4となる場合である。この
ようなドツト配列が存在すると、斜め方向のドツト間隔
を補間することによりCの部分がつぶれてしまう可能性
がある。
Figures 3 to S show examples of key patterns that cause "one collapse of a character" due to concentration of dots in the original pattern of the character. Figure 3 shows an arbitrary lattice point of the complementary set of lattice point C (centered on lattice point C), and the number n of upper, lower, left and right dossi (shaded) is 4. If such a dot arrangement exists, there is a possibility that the portion C will be crushed by interpolating the dot spacing in the diagonal direction.

第4図(a)Jb)はnx3の場合であって、(a)で
は格子点CK隣接するドラF数が最小となり。
FIG. 4 (a) Jb) shows the case of nx3, and in (a), the number of grid points CK and adjacent grid points F is the minimum.

(b)では最大となる(斜め方向も含める)。In (b), it is maximum (including diagonal directions).

第5図(a)、(b)はn = 2の場合であり、(a
)。
Figures 5(a) and (b) are for n = 2, and (a
).

(b)はそれぞれ隣接ドラF数が最小、最大の状態であ
る。ここで、第4図(b)および第す図(b)のパター
ンは、ドツトの平行配列における中央の白色部分を補間
によりりぶし℃しまう可能性がある。
(b) is a state in which the number of adjacent driver F is minimum and maximum, respectively. Here, in the patterns shown in FIGS. 4(b) and 4(b), there is a possibility that the white part at the center of the parallel arrangement of dots may be covered by interpolation.

したがって、第3図、第4図(b)および第5図(b)
  t−補間を実行しないキーパターンとして1重複ド
ツト印字方弐に適用することにより文字品質の劣化を防
ぐことができる。
Therefore, FIGS. 3, 4(b) and 5(b)
By applying this to the single overlapping dot printing method as a key pattern that does not perform t-interpolation, deterioration in character quality can be prevented.

次に%前述した補間を実行しないパターンを判定する補
間選択回路の構成について述べる。
Next, the configuration of an interpolation selection circuit that determines a pattern in which the above-mentioned interpolation is not performed will be described.

第6図は探索点の座標を示す、探索点C′は前述したよ
うに、原パターンの補集合の格子点Cの一つである。禅
索点C’に隣接する格子点座標を第6図の1〜Bのよう
に、すなわち、K(+1.−1)。
FIG. 6 shows the coordinates of the search point. As mentioned above, the search point C' is one of the grid points C of the complementary set of the original pattern. The coordinates of the lattice points adjacent to the grid point C' are as shown in 1 to B in FIG. 6, that is, K(+1.-1).

K(0,−1)、K(−1,−1)、K(−1゜0 )
、K(−1,+I L K(0,+1 )、K(+1.
+1 )eおよびK(+1.O)と規定する。
K(0,-1), K(-1,-1), K(-1゜0)
, K(-1,+I L K(0,+1), K(+1.
+1)e and K(+1.O).

なお、s素点dの点座標なK(0,0)とする。Note that the point coordinates of s raw point d are K(0,0).

このとき、第3図、第4図(b)、第5図(b)のキー
パターンのいずれかを判定する状態信号Kcは次の論理
で表わされる。
At this time, the state signal Kc for determining one of the key patterns shown in FIG. 3, FIG. 4(b), and FIG. 5(b) is expressed by the following logic.

Kc:I:ムncD+Adddinco+ANcp+ム
BCD+ABCD+ABCD +ABCD+ABCD+ABCD ) =ABCD+A’B’σD’(スCD+A]TD+AB
C+BCD)   ・・・・・・・・・・・・・・・・
・・(1)ここで、 A=cK(0,−1)、B=K(
−1,O)C=aK(0,+1 )、D=K(+1.0
 )A′=K(+1.−1 )、B’=K (−1,−
1)C’=K(−1,+1)、 D’=K(+1.−1
)Kcが@1′であれば補間は行なわない、探索点dは
、格子座標軸IおよびJ方向に走査することにより移動
する。第(1)式の論理表現を処理する回路の構成例を
第7図に示す。処理回路は’r!TLゲー)により簡単
に構成されることがわかる。
Kc:I:MncD+Addinco+ANcp+MuBCD+ABCD+ABCD +ABCD+ABCD+ABCD) =ABCD+A'B'σD'(SCD+A]TD+AB
C+BCD) ・・・・・・・・・・・・・・・
...(1) Here, A=cK(0,-1), B=K(
-1,O)C=aK(0,+1),D=K(+1.0
)A'=K(+1.-1), B'=K(-1,-
1) C'=K(-1,+1), D'=K(+1.-1
) If Kc is @1', no interpolation is performed, and the search point d is moved by scanning in the grid coordinate axes I and J directions. FIG. 7 shows an example of the configuration of a circuit that processes the logical expression of equation (1). The processing circuit is 'r! It can be seen that it can be easily configured by using TL game.

第7図において% 01 e J e G@はアンドゲ
ートs G、# 04 e G@ tおよびG、はイン
ヒビツシグーシsQqおよびG、はオアグーFである。
In FIG. 7, % 01 e J e G@ is AND gate s G, # 04 e G@ t and G, inhibit sQq and G, and OAG F.

次に動作を簡単に説明する。Next, the operation will be briefly explained.

アンドゲートG、の入力にはA、B、C,Dが入力され
るので、第(1)式の第1項の演算、すなわち、(AB
CD)が奥行され、結果が11″であればオアゲートG
、から@l 1 #が出力されるので。
Since A, B, C, and D are input to the AND gate G, the operation of the first term of equation (1), that is, (AB
CD) is depthed, and if the result is 11″, then the ORGATE G
, since @l 1 # is output.

補間は行われない、また、アンドグー)G、icはp:
、 B’、 c’、 r;が入力されるので、第(12
式の第2項の(i B’C’D’)の演算が行われ、そ
の結果がアンドグー)G、の入力の一方に加わる。また
、インヒビツFゲー)G1〜G、では、それぞれにmい
て、(XCD)、  〔Amo〕、(ABC)。
No interpolation is performed, and andgoo)G, ic is p:
, B', c', r;, so the (12th
The second term of the equation (i B'C'D') is calculated, and the result is added to one of the inputs of ANDG. Also, for Inhibit F Game) G1-G, (XCD), [Amo], (ABC).

および(ncfj)の演算が行われ、そのうち1つでも
@1”があれば、これがオアゲートG、を通ってアンド
ゲートG、の入力の他方に加わる。その結果、アンドゲ
ートG、からl11′が出て、これがオアグー)G、か
ら出力される。したがって、補間は行われない。
and (ncfj) are performed, and if even one of them is @1", it passes through the or gate G and is added to the other input of the AND gate G. As a result, l11' is input from the AND gate G. This is the output from OAG)G.Therefore, no interpolation is performed.

第8図はこの発明の一実施例の構成を示すプルツク図で
ある。この図で、11は7オントメモリで、原パターン
が記憶されている。12は補間回路であり、7オンFメ
モリ11の情報をもとに、重複させる場合の7オンFを
作る。13はセレクタで、補間するかどうかを選択する
。14は行バッファで、1行数分を記憶する。1Sはノ
ーンi制御系で、行バツフア14&c従って−・ンマ(
図示せず)を駆動し、所要の印字を行う、16はこの発
明の要部である補間選択回路で、第7図で説明した機能
のものであり、7オンFメモシ11の原パターンを検討
し1文字ととに補間するかしないかを決定し、セレクタ
1st駆動して、補間回路12を作動させるか、作動さ
せないかして、補間させたり、補間な止めたりして1文
字品質の良い印字を行わせる。
FIG. 8 is a pull diagram showing the configuration of an embodiment of the present invention. In this figure, 11 is a 7-ont memory in which the original pattern is stored. Reference numeral 12 denotes an interpolation circuit, which creates 7-on-F for duplication based on the information in the 7-on-F memory 11. 13 is a selector for selecting whether or not to perform interpolation. 14 is a line buffer that stores one line. 1S is a non-i control system, and the row buffer 14&c is therefore -・mma(
16 is an interpolation selection circuit which is the main part of this invention, and has the function explained in FIG. Decide whether to interpolate or not for one character, drive the selector 1st, activate or deactivate the interpolation circuit 12, and interpolate or stop interpolation to obtain a single character with good quality. Allow printing to occur.

なお、補間させるか、させないかの判断は、上記の実施
例に限定されるものではない。
Note that the determination of whether to interpolate or not is not limited to the above embodiment.

以上詳細に説明したように、この発明は簡単な補間選択
回路により複雑な文字パターンの重複の可否を判定する
ことができ、重複ドラ)印字にともな5文字品質の劣化
を防ぐことができる利点を有する。
As explained in detail above, the present invention has the advantage of being able to determine whether or not complex character patterns overlap using a simple interpolation selection circuit, and preventing deterioration of character quality due to printing of duplicates. has.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は重複ドラF印字方式の原理図、第2図(a)、
 (b)、 (e)、(d)は重複ドラ)印字による文
字品質の変化を示す図、第3図、第4図(a)、(b)
、第!1図(a)@(b)G!補間の可否を判定するキ
ーパターンを示す図、第61EIは探索点の説明図、第
7図はこの発W14による補間選定回路の構成例を示す
図、第8図はこの発明の一実施例を示すブロック図であ
る。 図中、Cは格子点、C′は探索点、1〜8は探索点C′
に隣接する格子点、11はフオンYメモリ、11は補間
回路、ISはセレクタ、14は行バッファ、1sはハン
マ制御系、16は補間選択回路である。 第3図 第4図 (a)                (b)第5図 (a)      (b) 第6図 一一一→−」 第7図
Figure 1 is a diagram of the principle of the double-drill F printing method, Figure 2 (a),
(b), (e), and (d) are duplicates) Diagrams showing changes in character quality due to printing, Figures 3 and 4 (a), (b)
, No. ! Figure 1 (a) @ (b) G! A diagram showing a key pattern for determining whether or not interpolation is possible, No. 61EI is an explanatory diagram of search points, FIG. FIG. In the figure, C is a grid point, C' is a search point, and 1 to 8 are search points C'
, 11 is an interpolation circuit, IS is a selector, 14 is a row buffer, 1s is a hammer control system, and 16 is an interpolation selection circuit. Figure 3 Figure 4 (a) (b) Figure 5 (a) (b) Figure 6 111→-'' Figure 7

Claims (1)

【特許請求の範囲】[Claims] 文字をマトリクス格子点におけるドツトの集合により形
成し、その文字のパターンのうち、格子間隔の大きい隣
接したトッド間隔を複数のドツトにより補間する重複ド
ツト印字装置において、補間対象となる格子点に関し、
上下、左右および斜め方向の隣接する格子点におけるド
ツトの存在により補間実行の選択を行う補間選択回路を
具備せしめたことV4?黴とする重複ドツト印字装置。
In an overlapping dot printing device that forms characters by a collection of dots at matrix lattice points, and interpolates adjacent tod intervals with large lattice intervals among the character patterns using a plurality of dots, regarding the lattice points to be interpolated,
V4? What is provided is an interpolation selection circuit that selects interpolation execution based on the presence of dots at adjacent grid points in the vertical, horizontal, and diagonal directions. Duplicate dot printing device that produces mold.
JP56123587A 1981-08-08 1981-08-08 Overlapping dot printer Granted JPS5825968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56123587A JPS5825968A (en) 1981-08-08 1981-08-08 Overlapping dot printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56123587A JPS5825968A (en) 1981-08-08 1981-08-08 Overlapping dot printer

Publications (2)

Publication Number Publication Date
JPS5825968A true JPS5825968A (en) 1983-02-16
JPH0216219B2 JPH0216219B2 (en) 1990-04-16

Family

ID=14864279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56123587A Granted JPS5825968A (en) 1981-08-08 1981-08-08 Overlapping dot printer

Country Status (1)

Country Link
JP (1) JPS5825968A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027552A (en) * 1983-07-26 1985-02-12 Oki Electric Ind Co Ltd Printing system for dot printer
JPS60225762A (en) * 1984-04-20 1985-11-11 レックスマーク・インターナショナル・インコーポレーテッド Printing device
JPS629960A (en) * 1985-07-03 1987-01-17 レックスマーク・インターナショナル・インコーポレーテッド High-density display method of dot-matrix character

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6338312A (en) * 1986-07-29 1988-02-18 エスジ−エス・マイクロエレットロニカ・エス・ピ−・エ− Voltage repeater circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6338312A (en) * 1986-07-29 1988-02-18 エスジ−エス・マイクロエレットロニカ・エス・ピ−・エ− Voltage repeater circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027552A (en) * 1983-07-26 1985-02-12 Oki Electric Ind Co Ltd Printing system for dot printer
JPH0457510B2 (en) * 1983-07-26 1992-09-11 Oki Electric Ind Co Ltd
JPS60225762A (en) * 1984-04-20 1985-11-11 レックスマーク・インターナショナル・インコーポレーテッド Printing device
JPS60239252A (en) * 1984-04-20 1985-11-28 レックスマーク・インターナショナル・インコーポレーテッド Printer
JPS629960A (en) * 1985-07-03 1987-01-17 レックスマーク・インターナショナル・インコーポレーテッド High-density display method of dot-matrix character
JPH0457195B2 (en) * 1985-07-03 1992-09-10 Retsukusumaaku Intern Inc

Also Published As

Publication number Publication date
JPH0216219B2 (en) 1990-04-16

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