JPS58222349A - Information processor - Google Patents

Abstract

PURPOSE:To reduce remarkably the power consumption, by providing a mask register masking an interruption request for stopping the selection of an interruption request source and the supply of clock to other interruption request source. CONSTITUTION:Suppose that only an external interrupting request is not masked and all other interrupting requests are masked, for example. That is, a mask register bit 9-1 is reset and 9-2, 9-3 are set. The processing section discriminates that there is no need of processing, a stop state HALT instruction is executed and sets a set/reset FF 11. This output Q is inputted to a HALT control circuit 7 to set HALT. An output Q' is a low level, an output of OR circuits 12-2, 12-3 goes to a low level, AND circuits 13-2, 13-3 are not established and the transmission of clock is blocked. That is, the action of a timer circuit 3 and an interface circuit 4 are stopped. Further, since outputs of AND circuits 8-2, 8-3 are also in low level, the release of HALT is inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to an information processing apparatus having an interrupt processing function.

In recent years, there has been a strong demand for lower power consumption in information processing devices such as microcomputers. The effect of lower power consumption is to reduce the cost and make the power supply part of battery-powered and applied systems more compact, and because it generates less heat, it increases the thermal reliability of applied systems and enables high-density mounting in limited space. For example, it makes it possible to

Usually, in order to satisfy the above requirements, a technique is used in which a microcomputer is constructed from a complementary metal oxide film semiconductor circuit (hereinafter referred to as 0M08 circuit). Generally 0M0
In the 8 circuit, the current that charges and discharges the load capacitance only flows through the circuit when the output changes, so it can be used as an N channel, channel or P channel.
It is well known that the power consumption is significantly lower than that of a metal oxide film semiconductor circuit with a single channel, and that the power consumption is almost zero in a steady state with a fixed output, especially when configured with a static circuit. Therefore, by taking advantage of this advantage, during free time when there is no need to perform microcombi Hoshi-Taka processing, the circuit can be controlled in a predetermined manner without supplying 4-tsuku (operation timing control signals) to major processing blocks such as arithmetic and control circuits. It is generally done to stop the machine in the state of □. This stopped state (hereinafter referred to as "HAL")
In the T state), most circuits do not operate because no clock is supplied. Therefore, it is possible to stop processing until the first processing request with low power consumption occurs.

In general, processing requests are made using internal or external interrupts, and when any interrupt occurs, the HALT state is released, clock supply is resumed, and the normal operating state is restored.

Therefore, in order to release this HALT state, all the multiple interrupt generation internal circuits (hereinafter referred to as interrupt generation sources) prepared inside the microcomputer must be activated.
It is necessary to continue supplying clocks even during the HALT period to maintain them in an operating state.

Conventional microcomputers that have this kind of function cannot select an interrupt request to release the HALT state, so if an interrupt occurs, it is inevitable that the HALT
The state was 〒, removed i′″″ configuration. As a result, the p ) iALT state is canceled due to the inadvertent occurrence of an interrupt.
AwJ's work has caused damage to application systems, and has the disadvantage that the processing section is occupied by unnecessary execution of interrupt processing, and there is a high risk that urgent processing requests will be ignored and fc errors occur. Furthermore, since it is necessary to supply clocks to all interrupt generation sources and keep them operating even in the HA-LT state, there is also a drawback that unnecessary power consumption is caused in unnecessary interrupt generation sources.

In application fields that use the HALT state, the type of interrupt used to release the HALT state can often be specified, such as an external key input interrupt or an internal timer interrupt, in which case other interrupt generation sources are rarely used. is common. Therefore, especially in microcomputers having many interrupt generation sources, losses due to this drawback are significant.

An object of the present invention is to provide an information processing system that can provide multiple interrupt sources with low power consumption.

The information processing device of the present invention is characterized by significantly reducing power consumption by providing a means for selecting only a desired interrupt source and a means for stopping clock supply to other interrupt sources. do.

In the present invention, in a system that has a peripheral device or an internal circuit that can generate interrupt requests, and has a function of executing interrupt processing in response to those interrupt requests,
A processing unit that executes interrupt processing, a HALT control circuit that temporarily stops this operation, and a HALT control circuit that selects only a desired interrupt request in the HALT state and supplies clocks to the peripheral devices or internal circuits corresponding to other interrupt requests. and a mask control circuit that stops, and in the HALT state, the HALT state is canceled by an interrupt request selected by the mask control circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of its main parts. 1 is program memory (e.g. read-only memory)
This is a memory unit that includes a data memory (for example, a random access memory) and a data memory (for example, a random access memory). 2 is a processing section including various registers and an arithmetic control circuit. 3 is a timer circuit, and 4 is an interface circuit for inputting and outputting data with other microcomputers, peripheral devices, etc.

In this example, serial data transfer is shown, but of course parallel data transfer may also be used. 5 is an external interrupt detection circuit for the peripheral terminal device 100 in the system (for example,
It detects interrupt requests from keyboard terminals, etc.). Reference numeral 6 denotes a mask control circuit, into which are input an interrupt request signal INTT from the timer circuit 3, an interrupt request signal INTO from the serial interface circuit 4, and an interrupt request signal INTE from the external interrupt external circuit 5. outputs a signal to release the HALT state according to these input states and the state of the mask register provided inside the mask control circuit, and further outputs a signal to the timer circuit 3 to release the CO
CO to T signal serial interface circuit 4
8 signals and a COE signal to the external interrupt detection circuit 5, respectively. These COT, C08, and CUE signals become clock signals that control operation timing. 7 is internal 1
A HALT control circuit that controls to stop the operation of at least a part of the road and to cancel the stopped operation,
A part of the output end of the Mamaku control circuit 6 is connected.

Reference numeral 8 denotes an interrupt control circuit which inhibits and permits interrupts based on commands, and is a MOS input from the mask control circuit 6.

This circuit determines the priority of interrupt requests based on the states of the MOT and MOE signals, and issues an interrupt instruction to the processing unit based on the priority.

Next, details of the mask control circuit 6 are shown in FIG. 2, and will be explained using it. In FIG. 2, the above-mentioned interrupt request signals INTE, INTT, and INTS are each supplied to an AND circuit 8.
-1.8-2.8-3. Reference numeral 9 designates a mask register which has the function of selecting a desired interrupt request signal and stopping the clock supply to the circuit corresponding to the masked interrupt request during the HALT state. 9-1
, 9-2 and 9-3, the output of which is the inverted output of the register, and is connected to one input terminal of the corresponding ANDNi, 8 and OR circuit 12. The output of the AND circuit 8 is connected to the input terminal of the OR circuit 10,
Its output is connected to the reset input terminal of a set-reset slip-flop (hereinafter referred to as S'fLF/F) 11. A HALT command control signal 14 is supplied to the set input of the SRF/Fil so that it can be reset by a command for setting the HALT state (hereinafter referred to as a HALT command). Also, the output of the OR circuit 10 is led to the reset input, and the output Q of the 08RF/F11, which is reset by its high level output, controls the HALT control circuit 7, and when SRF/Fil is set, the HA
Set LT status. On the other hand, the output Q is an inverted output of the output Q, and is commonly applied to one input terminal of the OR circuit 12. When 8RF/Fil is set and the inverted output of the mask register 9 is at a low level, the output of the corresponding OR circuit 12 is at a low level, and the output of the AND circuit 13 to which its output end is connected is the other input. Always at low level regardless of the clock. Two sides, 8
When RF/Fil is reset, the output Q is not at a high level, and the output of the OR circuit 12 to which Q is connected is at the noy level regardless of the other input. Therefore, the AND circuit 13
A signal equal to the clock signal is output. In addition, each output signal MOE, MO'l'', MOS of the AND circuit 8
is supplied to the interrupt control circuit and issues an interrupt request.

The interrupt control circuit is set by an interrupt enable instruction (hereinafter referred to as EI instruction) and an interrupt disable instruction (hereinafter referred to as DI instruction).
There is a clip-flop which is reset by a command (referred to as an instruction), and the priority order is determined based on the state of the flip-flop and the input state of the interrupt request, and necessary interrupt processing instructions are transmitted to the processing section.

Next, the setting and release of the HAL 'l' state and the operation of the interrupt control circuit will be explained as an example of a state where only external interrupt requests are not masked and all other interrupt requests are masked, that is, the mask register bit. 9-1 reset,
The case where 9-2.9-3 is set will be explained. When the processing unit determines that the processing is no longer necessary, it sets the contents of each mask register so that it can be canceled only by an external interrupt request, and sets the HALT state by executing the HALT instruction. p8RF/F' by executing the HALT command
11 is set and its output Q is high level fiHA
Generates a control signal to the LT control circuit. On the other hand, SR,I
! "The output Q of F11 becomes low level. At this time, the bits other than mask register bit 9-1 are set and are in the masked state, so the inverted output is low level. Therefore, the mask register bit 9-2, 9
The output of the OR circuit 12-2, 12-3 to which -3 is connected becomes low level because the output Q of the other input 8RF/Fll is low level. For this reason, the output of the AND circuit 13-2, 13-3 prevents the transmission of the clock, which is the other input, and becomes a low level, so that no clock signal is supplied to the timer circuit or the clear interface circuit. That is, the operations of the timer circuit 9 and the serial interface circuit are stopped in a predetermined state, and no power is consumed during that time. Also, mask register bit 9-2.9-
The output of the AND circuit 8-2, 8-3 to which 3 is connected becomes a low level regardless of the other inputs INTT and INTS, and release of the HALT state by the timer circuit and serial interface circuit is prohibited. At this time, the only interrupt source that is operating is the external interrupt detection circuit that can release the HALT state, so if the six interrupt sources consume equal power, the interrupt source according to this embodiment The power consumption is % of that when the present invention is not implemented, which is extremely low power consumption.

When an interrupt request is generated from, for example, a keyboard terminal of a peripheral terminal device in this state, the external interrupt detection circuit detects it and sets the INTE signal to a high level. In response to this, since the inverted output of the mask register 9-1 is at a high level, the output of the AND circuit 8-1 becomes a high level, and the output is propagated to the OR circuit 10f and 8RF/F1.
1-q Reset. As a result, the HALT state is released.

Furthermore, if the interrupt control circuit to which MOE, which is the output of the AND circuit 8-1, is connected is in the interrupt enabled state by the interrupt enable instruction at this time, the interrupt request will be sent as follows: Upon reception, an interrupt processing instruction is given to the processing section, and the processing section performs the interrupt processing in accordance with the instruction. However, if the interrupt is disabled due to the execution of the interrupt disable instruction, no interrupt processing instruction is given and only the HALT state is released.

In the above example, the case where the interrupt requests of the timer circuit and the serial interface circuit are masked by the mask register has been described, but the operation in other cases of INTT and INTS can be considered in the same way.

According to the present invention, by using a mask register that masks interrupt requests, it is possible to selectively release the HALT state and eliminate the possibility of malfunction of the application system due to inadvertent interrupt requests. Furthermore, by stopping the clock supply to the masked interrupt generation source, the source stops operating in a predetermined state, significantly reducing power consumption in the HALT state, and making it possible to efficiently control the HALT state. In particular, the present invention is extremely effective for watch microcomputers that receive periodic interrupt requests and do not need to operate in any other state, portable microcomputers that require extremely low power consumption, and the like. Furthermore, since there are many applications in which the device is powered by a battery and the device is stopped for a long time without turning off the power, the effects of the present invention are particularly significant.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing one embodiment of the present invention. 1...Memory section, 2...Processing section, 3.
...Timer circuit, 4 ... Serial interface circuit, 5 ... External interrupt detection circuit, 6 ... Mask control circuit, 7 ...... H.A.
LT control circuit, 8... Interrupt control circuit, 100
. . . Peripheral Terminal Device FIG. 2 is a circuit block diagram showing details of a mask control circuit according to an embodiment of the present invention. 8-1.8-2.8-3.13-1.13-2.13-
3...AND circuit, 9...Interrupt mask register, io. 12-1.12-2.12-3...OR circuit,
11...Set reset flip 70 knobs, 1
4...HALT command control signal.

Claims (1)

[Claims] A plurality of interrupt request sources, a processing unit that executes interrupt processing based on the requests, a means for selecting a predetermined interrupt request source, and a means for providing a clock to the selected interrupt request source and controlling the remaining interrupt request sources. An information processing apparatus comprising: a clock and a clock control means for stopping supply of a clock to an interrupt request source.