JPS58225657A - Multilayer hybrid integrated circuit - Google Patents
Multilayer hybrid integrated circuitInfo
- Publication number
- JPS58225657A JPS58225657A JP57107873A JP10787382A JPS58225657A JP S58225657 A JPS58225657 A JP S58225657A JP 57107873 A JP57107873 A JP 57107873A JP 10787382 A JP10787382 A JP 10787382A JP S58225657 A JPS58225657 A JP S58225657A
- Authority
- JP
- Japan
- Prior art keywords
- resistors
- laser
- conductive path
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は多層混成集積回路、特に抵抗体を多層化しレー
ザートリミングできる混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer hybrid integrated circuit, and particularly to a hybrid integrated circuit in which resistors are multilayered and can be laser trimmed.
従来の混成集積回路に於いて導電路の多層化については
数多(実施されている。しかしながら抵抗体の多層化に
ついては実現に至っていない。こねは混成集積回路に用
いるメタルグレーズ抵抗やカーボン抵抗を多層化すると
、多層化のための樹脂絶縁膜と反応して相溶しペースト
組成が失なわれ抵抗値が制御できな(なる欠点がある。In conventional hybrid integrated circuits, there have been many attempts to increase the number of layers of conductive paths. However, multilayering of resistors has not yet been realized. When multilayered, it reacts with the resin insulating film for multilayering, becomes compatible, and loses its paste composition, making it impossible to control the resistance value.
また多層化された抵抗体のトリミングが困難であり、抵
抗値の制御が難しい欠点がある。Furthermore, it is difficult to trim a multilayered resistor, and it is difficult to control the resistance value.
本発明は斯る欠点に鑑みてなされ、抵抗体の多層化を実
現する多層混成集積回路を実現するものである。以下に
図面を診照して本発明の実施例を詳述する。The present invention has been made in view of these drawbacks, and is intended to realize a multilayer hybrid integrated circuit that realizes multilayering of resistors. Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明に依る多層混成集積回路は図面に示す如く、混成
集積回路基板(1)と、該基板(1)上に設けた、声箔
より成る第1の導電路(2)と、第1の導電路(2)間
に無電解ニッケルメッキにより形成したニッケルメッキ
抵抗体(3)と、第1の導電路(2)およびニラ友ルメ
ノキ抵抗体(3)を被覆する耐レーザー保護樹脂層(4
)と、この樹脂層(4)上に設けられ孔(5)を介して
第1の導電路(2)と連結された第2の導電路(6)と
、第2の導電路(6)間に設けた第2のカーボン抵抗体
(7)より構成されている。As shown in the drawings, the multilayer hybrid integrated circuit according to the present invention includes a hybrid integrated circuit board (1), a first conductive path (2) made of voice foil provided on the board (1), and a first conductive path (2) made of a voice foil. A nickel-plated resistor (3) formed between the conductive paths (2) by electroless nickel plating, and a laser-resistant protective resin layer (4) covering the first conductive path (2) and the Chinese chive-like resistor (3).
), a second conductive path (6) provided on the resin layer (4) and connected to the first conductive path (2) via the hole (5), and a second conductive path (6). It is composed of a second carbon resistor (7) provided in between.
斯る構造に於いて、混成集積回路基板(1)とじてはセ
ラミックスあるいは表面をアルマイト処理したアルミニ
ウム基板等を用いる。In such a structure, the hybrid integrated circuit board (1) is made of ceramic or an aluminum substrate whose surface has been treated with alumite.
第1の導電路(2)は基板(1)の全面に貼着しだ銅箔
な選択エツチングして所望のパターンにして形成される
。The first conductive path (2) is formed on the entire surface of the substrate (1) by selectively etching a copper foil into a desired pattern.
第1のニッケルメッキ抵抗体(3)は基板(1)表面に
レジストをスクリーン印刷してその露出部分に無電解ニ
ッケルメッキして形成する。The first nickel-plated resistor (3) is formed by screen printing a resist on the surface of the substrate (1) and electroless nickel plating on the exposed portion.
耐レーザー保護樹脂層(4)は本発明の最も特徴とする
点であり、熱硬化性あるいは熱可塑性の有機物合成樹脂
中にレーザー光非透過性の無機物フィラーを分散して含
有させる電気絶縁材料である。The laser-resistant protective resin layer (4) is the most characteristic feature of the present invention, and is an electrically insulating material in which an inorganic filler that does not transmit laser light is dispersed in a thermosetting or thermoplastic organic synthetic resin. be.
熱硬化性樹脂としてはエポキシ樹脂を用い、無機物フィ
ラーとして窒化ボロン(BN)、アルミナ(A120.
)、メルク(3MgO・4SiO2・2H,O)等を一
種又は数種混合1−、て用いる。無機物フィラーは透過
レーザー光を散乱してエネルギー密度を低下させるので
、透過率50%以下であれば保護効果が得られ、る。Epoxy resin was used as the thermosetting resin, and boron nitride (BN) and alumina (A120.
), Merck (3MgO.4SiO2.2H,O), etc. are used singly or in combination. Since the inorganic filler scatters the transmitted laser light and lowers the energy density, a protective effect can be obtained if the transmittance is 50% or less.
斯上l〜だ耐レーザー保護樹脂層(4)はスクリーン印
刷して付着され、少くとも多層化を行う部分の第1のニ
ッケルメッキ抵抗体(3)および第1の導電路(2)を
完全に被覆1−る。なお第1の導電ji25 (2)と
の接続を行う孔(5)およびトランジスタ等の回路素子
(8)を固着する部分を除いて選択的にスクリーン印刷
を行う。The laser-resistant protective resin layer (4) is applied by screen printing and completely covers the first nickel-plated resistor (3) and the first conductive path (2), at least in the area where multilayering is to be performed. Coating 1-ru. Note that screen printing is selectively performed except for the hole (5) for connection with the first conductive ji25 (2) and the portion to which a circuit element (8) such as a transistor is fixed.
第2の導電路(6)は耐レーザー保護樹脂層(4)表面
に所望のパターンに形成される。第2の導電路(6)と
しては無電解ニッケルニッケルメッキで形成されるか、
あるいは欽ペーストのスクリーン印刷で形成される。な
おこの第2の導電路(6)を孔(5)上にも同時に形成
して第1の導電路(2)との連結を行う。The second conductive path (6) is formed in a desired pattern on the surface of the laser-resistant protective resin layer (4). The second conductive path (6) is formed by electroless nickel plating, or
Alternatively, it can be formed by screen printing with a paste. Note that this second conductive path (6) is also formed on the hole (5) at the same time to connect with the first conductive path (2).
第2の抵抗体(7)は耐レーザー保iI!樹脂層(4)
上の第2の導電路(6)間に形成される。第2の抵抗体
(7)はカーボン抵抗塗料をスクリーン印刷して焼成し
て形成する。斯る第2の抵抗体(7)はレーザー光によ
りトリミングを行い、所望の抵抗値に調整する。The second resistor (7) is laser resistant to II! Resin layer (4)
formed between the upper second conductive path (6). The second resistor (7) is formed by screen printing and baking carbon resistance paint. The second resistor (7) is trimmed with laser light and adjusted to a desired resistance value.
本11.オフ、一工程よ於い、−Cv−f−光、1カー
7.ッ ・1抵抗(7)を切断するが、耐レー
ザー保護樹脂層(4)でそのエネルギー密度は散乱され
、第1のニッケル抵抗体(3)および第1の導電路(2
)との絶縁を良好に保持できる。Book 11. Off, 1 step, -Cv-f-light, 1 car 7.・Although the first resistor (7) is cut, its energy density is scattered by the laser-resistant protective resin layer (4), and the first nickel resistor (3) and the first conductive path (2
) can maintain good insulation.
以−Fに詳述した如く本発明に依れば、抵抗体の多層化
を容易に実現でき且つ従来不可能とされていた上層の抵
抗体のレーザートリミングを行うことができる。この結
果混成集積回路の回路設計の自由度が増17、小型化に
寄与できる有益なものである。As described in detail in Section F above, according to the present invention, it is possible to easily realize a multi-layered resistor, and to perform laser trimming of the upper layer of the resistor, which was previously considered impossible. As a result, the degree of freedom in circuit design of the hybrid integrated circuit is increased17, which is beneficial as it can contribute to miniaturization.
図面は本発明による多層混成集積回路な説明する断面図
である。
主な図番の説明。
(1)は混成集積回路基板、(2)は第1の導電路、(
3)は第1のニッケルメッキ抵抗体、(4)は耐レーザ
ー保護樹脂層、(7)は第2の抵抗体である。The drawing is a cross-sectional view illustrating a multilayer hybrid integrated circuit according to the present invention. Explanation of main drawing numbers. (1) is a hybrid integrated circuit board, (2) is a first conductive path, (
3) is the first nickel-plated resistor, (4) is the laser-resistant protective resin layer, and (7) is the second resistor.
Claims (1)
電路間に設けた第1のニッケルメッキ抵抗体と、前記第
1の導電路およびニッケルメッキ抵抗体を被覆する耐レ
ーザー保護樹脂層と、該樹脂層上に設けられ孔を介して
前記第1の導電路と連結された第2の導電路と、該第2
の導電路間に設けたレーザートリミングされた第2のカ
ーボン抵抗体とを具備することを特徴とする多層混成集
積回路。1. A first conductive path on a hybrid integrated circuit board, a first nickel-plated resistor provided between the first conductive path, and a laser-resistant coating covering the first conductive path and the nickel-plated resistor. a protective resin layer; a second conductive path provided on the resin layer and connected to the first conductive path through a hole;
and a laser-trimmed second carbon resistor provided between the conductive paths of the multilayer hybrid integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57107873A JPS58225657A (en) | 1982-06-22 | 1982-06-22 | Multilayer hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57107873A JPS58225657A (en) | 1982-06-22 | 1982-06-22 | Multilayer hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58225657A true JPS58225657A (en) | 1983-12-27 |
JPH049382B2 JPH049382B2 (en) | 1992-02-20 |
Family
ID=14470248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57107873A Granted JPS58225657A (en) | 1982-06-22 | 1982-06-22 | Multilayer hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58225657A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63224392A (en) * | 1987-03-13 | 1988-09-19 | 日本メクトロン株式会社 | Multilayer printed interconnection board and method of processing the same |
JPH0249169U (en) * | 1988-09-29 | 1990-04-05 | ||
DE19807956B4 (en) * | 1997-02-26 | 2007-08-30 | Denso Corp., Kariya | Method for separating insulating substrates |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101833959B1 (en) | 2009-10-23 | 2018-03-02 | 다우 코닝 도레이 캄파니 리미티드 | Thickening agent or gelling agent for oil-based raw material |
CN102666664B (en) | 2009-10-23 | 2015-09-23 | 道康宁东丽株式会社 | The organopolysiloxane of modification altogether |
JP5754724B2 (en) | 2009-12-24 | 2015-07-29 | 東レ・ダウコーニング株式会社 | Cosmetic powder surface treatment agent, and cosmetics containing powder surface-treated with the cosmetic powder surface treatment agent |
CN102665668B (en) | 2009-12-24 | 2014-10-22 | 道康宁东丽株式会社 | Copolymer having carbosiloxane dendrimer structure, and composition and cosmetic containing the same |
US9980897B2 (en) | 2010-04-30 | 2018-05-29 | Dow Corning Toray Co., Ltd. | Organopolysiloxane and powder treatment agent, preparation for external use and cosmetic comprising the same |
WO2011136393A1 (en) | 2010-04-30 | 2011-11-03 | Dow Corning Toray Co., Ltd. | Organopolysiloxane and use thereof as surfactant, powder treatment agent, thickening agent of oil -based raw material or gelling agent. gel and emulsion compositions, as well as, preparations for external use and cosmetics comprising the same |
JP5856386B2 (en) | 2010-04-30 | 2016-02-09 | 東レ・ダウコーニング株式会社 | Powder treatment agent containing sugar alcohol-modified organopolysiloxane, powder surface-treated with the powder treatment agent, and raw materials for cosmetics and cosmetics containing them |
JP5830293B2 (en) | 2010-07-30 | 2015-12-09 | 東レ・ダウコーニング株式会社 | Hair cosmetic containing co-modified organopolysiloxane |
JP2013095835A (en) | 2011-10-31 | 2013-05-20 | Dow Corning Toray Co Ltd | Long chain amide-modified silicone/amino-modified silicone copolymer and use of the same |
JP6369888B2 (en) | 2011-12-27 | 2018-08-08 | 東レ・ダウコーニング株式会社 | Novel liquid organopolysiloxane and use thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS558096A (en) * | 1978-06-30 | 1980-01-21 | Ibm | Ic package |
-
1982
- 1982-06-22 JP JP57107873A patent/JPS58225657A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS558096A (en) * | 1978-06-30 | 1980-01-21 | Ibm | Ic package |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63224392A (en) * | 1987-03-13 | 1988-09-19 | 日本メクトロン株式会社 | Multilayer printed interconnection board and method of processing the same |
JPH0249169U (en) * | 1988-09-29 | 1990-04-05 | ||
DE19807956B4 (en) * | 1997-02-26 | 2007-08-30 | Denso Corp., Kariya | Method for separating insulating substrates |
Also Published As
Publication number | Publication date |
---|---|
JPH049382B2 (en) | 1992-02-20 |
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