JPS58215842A - Hunting accelerating type frame synchronizing system - Google Patents

Abstract

PURPOSE:To compensate out of synchronism effectively, by observing an output of a correlation detecting circuit continuously when the internal state of a state control circuit is in hunting state, and loading the prescribed number of the outputs to a counter circuit immediately when the coincidence of pattern is detected. CONSTITUTION:When the output of the correlation detecting circuit 3 shows the coincidence of pattern at the 1st observing time, the internal state is reset to the initial state. When the state of the output of the correlation detecting circuit 3 representing the dissidence of pattern is consecutive for a prescribed number of times at the 1st observing time or the output of the circuit 3 shows the coincidence of pattern even once at the 2nd observing time, the internal state is brought into the hunting state immediately. When the internal state of a state control circuit 4 is the hunting state, the output of the circuit 3 is observed continuously. Further, when the coincidence of pattern is detected, the prescribed number of outputs is loaded to the counter circuit 5 immediately. Thus, the number of times of out of synchronism due to a random error is decreased, and the system follows quickly a true out of synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a binary signal sequence with a clock period of T seconds that has a frame structure with a total (00m) bit length consisting of an n-bit length frame synchronization pattern and m-bit length information. The present invention relates to a frame synchronization method, and particularly relates to a frame synchronization method used in a situation where the probability that the same pattern as an n-bit length frame synchronization pattern will appear in m-bit length information is extremely low. That is, it relates to a unique word detection type frame synchronization method.

Such a unique word detection type frame synchronization method is often required in systems in which the phase fluctuation of the clock of a received binary coded signal sequence is large, such as a satellite communication system or a consumer digital sales system.

One of the most widely used unique word detection type frame synchronization methods is a method in which a detection window is provided. In this method, a temporal detection window is provided around the frame pulse position that currently indicates the correct frame position, and within this window, at each clock pulse generation point, n bits or n bits that have arrived up to that point are set. 2 of length below
Observe the value code sequence, determine whether the observed pattern thus obtained matches the synchronization pattern, and if
If a match is detected, the point at which the match is detected is immediately regarded as a new frame position. If a condition in which no matching pulse is found within the detection window continues for a prescribed number of N times, the system immediately enters a hunting state and searches for a new frame position. , the above-mentioned number of times N is a parameter called the so-called forward protection number of times.

The conventional method described above is effective when it is extremely unlikely that random errors caused by noise or the like will cause a coincident pulse to occur at a position shifted from the current frame position. To explain this, we will now write an n-bit-long synchronization pattern as (al, a, . . .
......Sa), m of the th frame
The bit length information pattern is (bk9. l b k,,
l・・・・・・・・・Evening, expressed as a). Then, the input binary code sequence is written as bk-f""... It is assumed that the detection window is ±3 bits, and that a frame pulse indicating the start of an m-bit information pattern in the first frame is at position bk,1. Then, the observation of the matching pattern is (J-t *,,1-t* bk-
1* m -1s b k-8'm' ” ' ”-
"%-s) and the reference pattern (a4.a2.....
・・・・Comparison with an) starts from ho, (a4*
al s"""...'wa a, e bll, 1 sbl
, t*bk, m) with the reference pattern. In this process, for example (bk -1' m, "1'
""-"3m+") is considered to match the reference pattern due to a random error, the current frame pulse is assumed to be at a position shifted by l bits from the normal position, and the new frame pulse position is set to al, l. change the position. As described above, in the conventional method, the forward protection function 5i is weakened against random errors within the detection window. In other words, in the conventional method, if a wide detection window is provided in order to achieve stable frame synchronization even in the face of clock phase fluctuations,
There is a kind of trade-off in that the forward protection function against random attacks is weakened accordingly.

The present invention solves the drawbacks of the conventional frame synchronization method as described above, and its principle is to focus on the peculiarity of the frame pattern, and to detect -C at a position different from the current frame position within the detection window. -C-original pulse +111. If so,
At that point, it is immediately assumed that 7 frames + 'Rf4k Z' have been lost, the thread is turned into a hunting pattern, and a new frame position is searched.

That is, the purpose of the present invention is to create a frame structure with a total length of (n+m) bits, consisting of a frame synchronization pattern with a length of 1dn bits and information with a length of 1η bits, with a clock period of T seconds.
In the frame synchronization method for signals, the number of clock pulses is calculated by the modulus (n0m), and the total is 2! Counting means that generates a frame pulse of time 1i1 T seconds each time the value reaches the specified 11σk, and n that has arrived by a certain observation point.
Observe the bit pattern of 'bits (where n' is a positive 'Ii number less than or equal to n), and the bit pattern thus obtained and
A correlation detecting means for detecting matching or mismatching of patterns by correlating with a predetermined 11'-bit reference pattern and the counting means are controlled according to the system state Jl! 4 control means, and if the internal state of the state control means is in the initial state, the position of the frame pulse that appears every (n+m) T seconds is the first observation time, and the first observation time is A second observation time having a predetermined time width is provided before and after the first observation time, and if the output of the correlation detection means indicates a pattern match in the first observation time, the internal state is initialized. state, and the state in which the output of the correlation detecting means shows a pattern mismatch continues for the current constant 8 times during the observation time of ^τ1, or the state in which the output of the correlation detecting means shows pattern mismatch during the second observation time If the output shows a pattern match even once, the internal state is immediately changed to the hunting state, and the "hidden" state is set to "ff?". When the internal state of the IJ wandering means is in a hunting state, the output of the correlation detection means is continuously observed, and a predetermined number k is loaded into the counting means immediately when a pattern match is detected. The objective is to provide a frame synchronization method that

The present invention will be explained below using the drawings. FIG. 1 is a block diagram showing a general embodiment of the frame synchronization system according to the present invention, in which 3 represents correlation detection means, 4 represents state control means, and 5 represents counting means. The correlation detection means 3 observes an input binary pattern of n' bits (where n' is a positive integer such that n'<n) that has arrived by a certain observation time, and combines the observed bit pattern and the reference bit pattern thus obtained. Correlation with the pattern is taken, it is determined whether or not a match with the reference pattern is obtained, and the determination result is transmitted to the state control means 4 via the signal line 6. Here, the observation time of the correlation detection means 3 is determined by a hunting command signal (hereinafter referred to as an H signal) given from the state control means 4 via the signal line 7 and a frame pulse given from the counting means 5 via the signal line 10. [This will be abbreviated as the F signal] and a count signal given from the counting means 5 via the signal line 9 (this will be abbreviated as the A signal).

That is, when the H signal is logic 10' (that is, when there is no hunting command), the time corresponding to 1 bit determined by the F signal is set as the first observation time, and it is obtained by the combination of the A signal and the F signal. The time corresponding to several bits before and after the F signal, ie, the detection window, is defined as the second observation time. There is no overlap between the tenth observation time and the second observation time. When the correlation detection means 3 detects a match at the first observation time, a state m is detected via the signal line 6.
The internal state of the ram means 4 is immediately changed to the initial state (this is called S
state). When the correlation detection means 3 detects a match at the second observation time, the internal state of the state control means 4 changes to the hunting state (hereinafter referred to as the H state) via the signal line 6. When the correlation detection means 3 detects a mismatch at observation time 1, the internal state of the state control means is changed via the signal line 6, but the transition of this internal state depends on how many mismatches occur after the S state. It depends on what you did. That is, if the number of forward protections is now 3, when one mismatch arrives after the S state, the internal state shifts to P1 state, bad, and when one more mismatch arrives, it shifts to P state. When one more discordance occurs in state P, this internal state changes to state H.

When the internal state of the state control means 4 becomes the H state, the correlation detection means 3 is supplied with an H signal of logic 11' via the signal line 7. When the H signal changes to logic ``1'', the correlation detection means 3 immediately tries to detect coincidence using all bit timing times as observation times. When a match is detected in this state, the state control means 4 resets its internal state to 8 states via the signal 8!6, and the counting means 5 always counts clock pulses for 17 frames. A load command (abbreviated as L signal) to a predetermined number is transmitted to the counting means 5 via the signal line 8 so as to generate a frame pulse at the time of the above-mentioned coincidence detection.

FIG. 2 is a state transition diagram showing the transition of the internal state of the state control means 4. As shown in FIG. 21, 22, 23, and 24 respectively represent the above eight states, P1 state) I, Pt state, and H state. Furthermore, 25.26.27 shows a state transition when a mismatch is detected at the first observation time. Furthermore, 29.30.31 shows the state transition when a match is detected at the first observation time.

32 represents the process of detecting a pattern in the hunting state and returning to the S state. The transition of 33.34°35 is during the second observation time, that is, the observation within the detection window.
It corresponds to the transition caused by detecting a match,
As can be seen from the figure, hunting is accelerated by matching detection within this detection window.

FIG. 3 is a waveform diagram illustrating the difference in resistance to random errors between the conventional frame synchronization method and the hunting accelerated frame synchronization method according to the present invention. In FIG. 3, the symbol represents a coincident pulse obtained by the correlation detecting means. Pulses 31 to 36 appear regularly at every frame synchronization. However, at position 35, a pulse is missing due to a random error. Pulse 37 is a coincident pulse generated at a position shifted forward from its original position due to a random error. 38.39 indicates that a correct coincidence pulse has occurred again. First, let us assume that it is in the conventional position of F\40. At this time, it is observed whether a matching pulse is included in the detection window 51, which is opened over several bits around 400 bits. In the example shown in the figure, when a matching pulse enters the detection window (3 times in the example shown in the figure), hunting starts, and when 33 matching pulses are detected, a frame pulse 43 is generated, and hunting ends. do.

Hereafter, 44. Regular frame pulses are generated every frame period as shown in numbers 5 and 46. Even if a coincident pulse is dropped due to random error 35, the frame pulse is not affected because forward protection is provided. Although it is inevitable,
When an erroneous matching pulse appears at a position shifted from the normal position due to a random error as shown in 37 and within the detection window, the frame pulse is shifted as shown in 47 by this pulse, and 47 (D y < A/ The next frame pulse 48 is generated at the new reference position.However, at this time, the coincidence pulse 38 generated at the normal position is
Since the pulse always falls within the detection window, a new frame position is determined as shown in 49, and frame pulses are generated every frame period thereafter. Therefore, if a coincident pulse is generated at a position deviated from the normal positional force due to a random error as in 37, a frame synchronization error for two frames will occur. That is, the conventional frame synchronization method does not have any forward protection W11 function for the generation of coincidence pulses due to random errors within the detection window. This is similar to the conventional frame synchronization method, but if there is an erroneous coincidence pulse due to a random error such as 37, hunting starts immediately from that point. Next match pulse 3
Since 8 is at the normal frame position, the resulting 7-frame pulse in the method of the present invention is 59.60.
61, the correct frame position can be maintained.

If the timing of the coincidence pulse is suddenly shifted due to a true bit shift rather than a random error, it is necessary to follow the new frame position as quickly as possible. In terms of followability, the conventional frame synchronization method is slightly better than the frame synchronization method according to the present invention. However, in actual systems, the influence of random errors9 is often more dominant, and furthermore, in the process in which the above-mentioned true P/F deviation occurs, false coincidence pulses due to random errors occur more frequently. . Therefore, in actual systems, the hunting accelerated frame synchronization method according to the present invention generally exhibits better synchronization characteristics.

? FIG. 4 is a circuit diagram showing a specific embodiment of the correlation detection means used in the hunting accelerated frame synchronization method of the present invention. In FIG. 4, the binary signal series inputted from the input terminal 70 is inputted to the serial input/parallel output type register 7B which reads data bit by bit using the clock pulse supplied from the terminal 74. The n'-bit parallel pattern obtained as an output is compared with an n'-bit reference pattern in a coincidence detection circuit 79.

That is, the - number output circuit 79 outputs a logic 1 code if the two match, and outputs a logic 0 if the two do not match.
Output. If this output is expressed as Q, Q is Angoo)
81 and 83, and the re-injection signal Q of Q is supplied to an AND gate 82. AND gate 8182 is terminal 73
Supplied by The opening and closing of the gate is controlled by a frame pulse (hereinafter referred to as an F signal) and a hunting command signal (hereinafter referred to as an H signal) supplied from a terminal 72. That is, the coincidence pulse detected during the period in which the idF signal or the H signal is logic "1" (hereinafter referred to as the R signal) is outputted to the output terminal 75, and the coincidence pulse detected during the period when the idF signal or the H signal is logic "1" is outputted to the output terminal 76.
The mismatched pulse (abbreviated as C signal) detected at the river is output. On the other hand, the AND gate 83 gates the output Q of the coincidence detection circuit 790 within the time set by the detection window setting circuit 80 and at a location where there is no frame pulse, and outputs the gated signal to the output terminal 77.

This signal will be called the C signal. Detection window setting circuit 8
0 looks at the count value supplied from the counting means 5 in FIG. logic"
1' to set the detection window.

FIG. 5 is a circuit diagram showing a specific embodiment of the state control means used in the present invention, in which 90° 91 and 92 are input points for the C signal, C signal, and ratio signal, respectively. An input terminal, 93 is an output terminal from which the above-mentioned H signal is output, 94
97.99 is an AND gate, 98 is an OR gate, 95 is a set-reset type flip 70 knob, and 96 is a counter. It is.

In the figure, a counter 96 normally counts C signals, that is, non-coincidence pulses, but is reset by R signals, that is, coincidence pulses. Also, the flip 70 knob 95 is set by the C signal, that is, the coincidence pulse within the detection window, and its output changes to high level, or the counter 96 is set to a specified count value (this corresponds to the number of forward protections). ) and its output changes to high level, the OR gate 98
The H signal obtained as the output immediately changes to a high level and issues a hunting command to the correlation detection means.

At this time, the C signal is inhibited by the AND gate 97.
The flip-flop 95 enters a state in which it waits for reset by the R signal. That is, when the matching pulse in the hunting state is input as the R signal, the 7 lip filter 95. The counter 96 is also reset, and the system returns to its initial state. Also,
At the time when a matching pulse is detected in the hunting process, the L signal obtained as the output of the AND gate 99 changes to a high level.

According to the present invention, the frequency of out-of-synchronization due to random errors can be reduced, and a hunting acceleration type frame can be used that can quickly follow true out-of-synchronization. Domei method % formula %

[Brief explanation of the drawing]

-m1 is a block diagram showing a general embodiment of the hunting acceleration type frame synchronization method according to the present invention, and is a state transition diagram and waveform diagram for explaining the operation of the hunting fern acceleration type frame synchronization method according to Akira Hon. . 4 and 5 are circuit diagrams respectively showing specific embodiments of the correlation detection means and state control means used in the hunting accelerated frame synchronization method according to the present invention, in which 78 is a register and 79 is a Coincidence detection circuit, 80, detection window setting circuit, 95
is a flip-flop, and 96 is a counter.

Claims (1)

[Claims] In a frame synchronization method for a binary signal with a clock period of T seconds that follows a frame structure with a total length of (n+m) bits consisting of a frame synchronization pattern with a length of n bits and information with a length of 01 bits, the number of clock pulses is modulo (n+m). counting means that generates a frame pulse of time width T seconds each time the counted value reaches a specified value K, and n' bits that have arrived up to a certain observation point (where n / is less than or equal to a correlation detection means for detecting a match or mismatch of patterns by observing a bit pattern of a positive integer and correlating the bit pattern thus obtained with a predetermined reference/gturn of n'bits; It includes a state control means for controlling the counting means according to the state of the system, and if the internal state of the state control means is in the initial state (n + m)
A second observation time 1111 in which the position of the seven pulses that appear every 'l' seconds is the first observation time, and a predetermined time span is observed before and after the first observation time.
If the output of the correlation detection means shows a pattern match at the first (f) observation time, reset the internal situation meeting to the initial state, and at the first observation time, perform the four
The state in which the output of the relationship detection means indicates pattern mismatch is the specified number N [i! If the output of the correlation detecting means shows a pattern match even once during consecutive E or the second observation time, the internal state (IL4) is immediately set to the hunting state, and the state control means When the internal state is in a hunting state, the output of the correlation detection means is continuously observed, and when a pattern match is detected, a predetermined number of Ki is immediately loaded into the i1" number means. Synchronous method.