JPS58196765A - Binary coding device of picture signal - Google Patents

Abstract

PURPOSE:To code character, etc., into binary values accurately by setting a slice level to an intermediate level between the peak value of the black level of a momentarily varying picture signal and the peak value of the white level. CONSTITUTION:An analog picture signal input is converted by an A/D converter 5 into a multilevel quantized digital picture signal, which is supplied to a comparator 12 through a delay circuit 13 and also sent to a black level peak holding circuit 6 and a white level peak holding circuit 7. The outputs of the peak holding circuits 6 and 7 are processed by a subtracting circuit 8, multiplying circuit 9, and adding circuit 11, whose output is supplied to the comparator 12. Then, the comparator 12 outputs a binary coded picture signal.

Description

[Detailed Description of the Invention] Image 1 suitable for image signal processing of the present invention 1, 7 Akzoz 'J, etc.:! Regarding the I-200 million device, Zara (for details,
This invention relates to a device that accurately binarizes documents with low density such as those marked with a pencil, characters printed on a colored background, or single white characters.

In the past, many image signal binarization circuits have been proposed, and one example of a typical configuration is shown in FIG.

In the conventional example vc'Jd shown in Figure 1, the image value obtained from an imaging means (not shown) is applied to the comparator circuit l, and is also input to the envelope detector tHL JK, where it is applied at an appropriate time. The envelope of the white level by the half-wave rectifier circuit RC with
will be inspected. He divided the envelope output by resistors using a voltage divider circuit 3, and added an off-cent voltage using a DC addition circuit to avoid picking up noise in the black background.

Comparison [94%/K is applied as a reference voltage, and the image signal is then binarized.

In the conventional example, the envelope detector is a black level peak hold circuit and has a temperature function, but it is known to have a drawback that it has a subtle effect on image quality depending on how the foot is set during discharge. . Also.

Furthermore, in Figure 1, it is assumed that the black background level of the document is at 1 ground potential, and therefore, ? F! There is a circuit that clamps to the ground potential at the black ground level in 47'11! Tona
There was a drawback. It was. #L-stream addition circuit tIVc 1 Since the offset electric ratio is simply added, the binary conversion of the white q] character was not satisfactory.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate these conventional drawbacks and provide an I# image signal binarization device.

Another object of the present invention is to digitize the arithmetic circuit for binarization, and to provide an image signal binarization device that requires no adjustment and has high performance.

Conventionally, only white level fluctuations were dealt with using an envelope detector, but in the present invention, one additional black level peak hold circuit is provided to deal with black level fluctuations as well. to perform accurate binarization processing.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

Figure 2 shows l! according to the present invention yc! FIG. 2 is a diagram of an embodiment of II@signal duplexing device. In the same figure, [%j is A-
It is a D converter. The binarization circuit described below can be implemented in either analog or digital form,
Cut the circuit below and cut the digital thread (:G'!
A-D conversion tj s is used. On the other hand.

When using the following circuits as analog threads, VC & Go, A
-D converter j may not be used. With an explanation in my free time! j,
A case will be explained in which the circuit shown in FIG. λ is entirely composed of digital circuits.

Analog II! The i-image signal input is converted into a multi-level blurred digital image signal V by the vtlA-D converter S, and its black level peak iiB is sampled and held by the black level peak hold circuit 4. On the other hand, the peak value W of the white level in the digital image i'gsv is sampled and held by the own level peak hold circuit 7. These sampled and held signals B and W are subtracted by a subtraction path IK, resulting in a difference signal B-W%:N. Next, the difference signal B-WK is added from the 1 multiplication circuit 9 and the constant circuit IOVC to the constant.
is multiplied, and the multiplication output yields (B-W)Y. here,
It is preferable to set the value to approximately 0.1.

The multiplication output k(B-W) and the white level peak value W from the white level peak hold circuit 7 are
and as the slice level T, T=kB +
(/-k)W (1) is obtained.

The reference signal T1. obtained as a result of the above calculation. *Statue I No. 3 V
Beak i + fi B of the black level and peak value W of the white level.

k: (/-5t) (2) Since the average addition is 1 time, accurate binarization can be performed. For example, if k is O, S, then k: (/-k)=0. j: (/-0,1)-/
: /(5), and the value of slice level T is located exactly in the middle between B and W.

Next, slice level T and digital image signal delay circuit 73! Supply the delayed output V obtained by s to a comparator/λ, and compare the magnitudes of T, V*, and t here to obtain a binarized signal. Since the signal is delayed by the black level peak hold circuit 6 and the white level peak hold circuit 7, the j ill i times N/3 are inserted for time alignment. The fist represents a delay operator.

Note that it is also possible to detect the image information that should have the value v#Ie for one number and automatically add it. For example, depending on the peak value of your own level, set the constant k to town f [and Keyaki is colored ground ■
- In the case of a statue with a cursive line or a ship's handwriting, the first one is a little closer to the black level (and the slice level is 1 more. By setting this, a more suitable binarization operation can be performed.

FIG. 3 shows a more detailed example of the embodiment of the invention shown in the silk coat.
Shows route a. Here, one A-D converter 41-# is omitted, but it corresponds to No. J-, and is all a digital Cedar type drifting circuit.

As a matter of fact, the digital image signal V is
- The change in the image signal between successive λ pixels is detected by a comparator J/ with a corresponding delay. A of comparator J/
The image signal of l-prime frame is input to the input 1, and B
The image signal of the current pixel is input to the input, and by determining the magnitude of the D, III signal level,
You can tell whether the BE is increasing, decreasing, or remaining constant.

Now, when the image signal is in an increasing state, in other words, it gradually becomes black over the course of an hour.
Since the A>8 output of comparator Jl becomes high level,
AND gate J# opens and clock CK r is driven to launch 32, and launches to 01 image signal vvk launch 32. Next, when the image signal turns into a decreasing state, that is, it gradually passes the black peak level. The blade turns white, and the core Halator 3/A > 8 output becomes low level, and the AND gate 3 closes, and the output terminal Q of the ratte 32
[i2 Black peak level is maintained.

At the same time, the low level A)B output is inverted by the E/(-ta 36), which opens the AND gate, so that the black peak level is also launched to the output Q of the error output n.

Next, the peak level of black starts to rise if 1f (when the 1st scale increases again to 1xJ, 7 q u +s order σ). Seven Pavilions, Lunch 3 Before the black peak level BY: It becomes the maintained t. In one example, (
The black peak hold circuit 6 is comprised of the 5th point 30, 32jI5 and the 5th point 30, 32jI5 and the 341 and 35th block, and the 5th block 341 and 35, and the peak hold circuit 6 in black.

On the other hand, the white peak hold circuit 7 is set to 1. Lunch n and 1g, andgate n and #0. and an inverter nail, and its operation and construction is similar to that of the black peak hold circuit 6 described above, but the AND gate J? The output A of the controller 31 is used to open and close H and 9.
<B'1: The only difference is that 6, sco peak hold signal BtX is directly supplied to adder #3, and the white peak hold signal Wk is supplied to adder #3 via inverter p. Is the operation of B-w real? 'T will be done. The B-W output of 7 is supplied to the doubler circuit. As for the case, 111 pieces of paper are used, and a multiplier is used, but for the sake of simplicity, here 1 piece = % binding hair, h times the number of circuits (・te% of B-W output) Full focus Y L8B m to l
Just by shifting the focus one by one, you can achieve h times (B-W). It is rather convenient because the slicing level is exactly in the middle of the black peak level and the white peak level.

Adder as vc Franch K (JJ W output and h circuit cup's (B-W)/λ output and Wl(B-W)
/coni(a+w)/a is calculated. This (B+ko)/
With the λ output as the slice level T, the comparator Kinuta's 8
Apply to input terminal. Comparator % A input terminal &'
A digital image signal V is applied to T, which is delayed by two pixels by L, C, and Q. This digital image signal ve&end is sliced at the slice level T to become a binary image signal.

Regarding lunch C and IJIc, in this example, if there are two, Y
Although the example has been given, it is not necessary to limit the number of lunches to λ-, and it is preferable to find an optimal number in the range of 0 to 5 based on the slew rate of rMm multiplier V. For example, if the number of birth focus points (%Image Note Vt1) is m (Bit) and the maximum slew rate is s (stt/P@l), the required number of D-car runners is (Conn11+l).
) is preferably set to -f. This result is obtained by detecting the peak value of white and &1 black, and from the idea of making it to the true Q) slice level, the desired Q is obtained even if the number of runners is 0. ) The performance can be fully demonstrated.

In the example shown in FIG. 2, the configuration shown in the figure was used to faithfully execute the calculation of equation (1).
) Of course, other configurations may be used as long as they satisfy the results.

For example, even if it is k-% (as it is sufficient to simply find the average of B and W, the configuration shown in FIG. 1) is acceptable. In other words, in Fig.

/4t &1 JJ[] is an arithmetic circuit, which adds the outputs B and W from peak hold circuits 6 and 7, and calculates the 111 calculated output tBW) as h's Sakae ml path 15 rC
(B+W)/λ output. In this example, the other parts can be made into the constituent elements of Figure 1 and ll1y1, so they are given the symbols ``xr corresponding Pk K kry10''-, and the details of those ) are omitted. .

ff In the embodiment shown in FIG. 1, for example, the adder circuit/I ks is replaced with the subtracter circuit 16 as shown in FIG. output 7) and the output W of the white level peak hold circuit 7
5C1
It's okay. With this configuration, the required number of focuses of comparator/2 can be reduced. In this example as well, the same reference numerals are given to the same reference numerals as in the example of FIG. 2, and their details are omitted.

In the image signal binarization circuit according to the present invention shown in FIG. 3, the riminter 'If! :Can be provided. - As an example, a non-1m function was written between launch 3 and launch 33 shown in Figure 3) tOM (
By inserting a read-only memory (read-only memory) Y, a data transfer operation can be performed. For example, as shown in Figure 6(A), 3 lunches and 2000 latte IIJ1 are stored in an ILOM with data t as shown in Figure 6(B). -By inserting a data conversion device, noise in continuous parts of black background can be removed (
It is J-Noh.

Even if there is a white background [j], it is possible to similarly provide a limiter with a white level peak hold circuit.

Image signal binarization circuit I construction according to the present invention shown in 11.
It can also be implemented with analog circuits. For example, in the diagram above, the delay circuit 73 can be configured digitally using a &7ft register, but it can be configured in an analog format.

For example, delay-in can be used to slow sailing. An analog comparator can be used as the magnitude co/parator 12. Da arithmetic circuit/fly,
For analog, a single VC resistor adder is sufficient.

As Eisan Circuit 9 &; Analog 5I! As the calculator 1, for example, MC/DA94CL manufactured by Motorola can be used.

The subtraction circuit r+s can be realized by a resistance addition circuit including a phase inversion circuit. Regarding the black V bell peak hold (b) circuit 6 and the own level peak hold circuit 7, for example, they can be constructed from analog circuits. Since these high voltage circuits 6 and 7 can be realized by the same circuit, only the one black level peak hold circuit will be explained here.

Fig. 7 rC O(・DE, SOt) FIT switch,
si finished: z/de/su, S2 is bread 7a increase @ device, S3
and j# is a delay line, jj and S6 are comparators.

S7 is an AND gate, and II is a delay line.

Analog image signal V is connected to delay line jJ and S4I
So, respectively, io! delayed by iI prime equivalent time,
Comparators jj and It_K are applied, respectively.

If the input-image signal at a certain time t is given by V (t), the way the delay lines jJ and j will appear is given by V (t - τ), where the delay time of each delay line is τ.
), V(t-coτ). The output of comparator sr becomes high level when V(t-τ)>V(t-2d), while the output of comparator j becomes vtt))
Since it becomes a high level when v(t-τ), the output of 57 becomes V(t))V(t-τn>v
It becomes high level when (t-coτ) (4). At that time, since the FIT input SO is turned on, the analog image signal gV (t) is stored in the capacitor 5iIC via the &1 delay line Elf. This equation (4) is the equation that gives the maximum value, and when the image signal does not exceed the above equation (4) 'k #, the FET input voltage is turned off, so the capacitor j/ The peak value will be sampled and held. The charge stored in the capacitor I/ is transmitted to the next stage as a black level peak hold signal B via a buffer amplifier S2. The delay line jl is a delay line for time adjustment inserted in order to accurately sample the value of V(t-τ) when it is at its maximum.

As described above, according to the present invention, the slice level can be set to, for example, an intermediate level between the peak value of the black level and the peak value of the white level of the image signal, which change from moment to moment. It is possible to accurately binarize minute characters, characters written on a single-color original VCIIF, characters that are thinly made such as ship's edge characters, and 1; white characters.

Moreover, unlike the conventional example, there is no need for a capacitor charging/discharging circuit, and stable binarization processing can be performed without the risk of the slice level changing over time. However, a binarization circuit composed only of digital circuits is suitable for integration into an integrated circuit.

This is also effective in reducing the size and cost of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of an image binarization circuit, FIG. 2 is a block diagram showing an example of an image signal binarization device according to the present invention, and FIG. A circuit diagram showing a more detailed circuit configuration of the digitization device, Figure S is a block diagram showing a second example of the image signal binarization circuit according to the present invention, and Figure S is a w4 image according to the present invention. A block diagram showing a third embodiment of the signal binarization device, FIG.
) is an explanatory diagram of an example of the ROM data, and FIG. 7 is a circuit diagram showing an embodiment of a black level peak hold circuit using an analog system. L... Comparison circuit, C... Envelope-detector. 3...Bunde(ro)ro, Da...Ii [rl
l adder circuit, j...AD change 1L 6...black level peak hold circuit, 7...white level peak hold circuit. l... - subtraction (b) circuit, ta... multiplication circuit,
10...constant circuit, //...addition circuit,
/2...-Comparator, /J...Delay time M,
l#...addition 11! ! lM, 15・
-Nine multiplication circuit. 16... Subtraction circuit, 30.32. n, 舊31. Rod, q... runner, 3t,
h... Comparator. j4+, 15. J'F, 匍...and gate. S6. II/...Inverter, 4Iλ・
...Inverter. #J, 113... Adder, Taku... h multiplication circuit. Cape...-Non-direct-data fly replacement fl (ROW), SO...
...FIT Suinte, 31...Capacitor. S2... Banfa intensifier, II, 14! ,5
1... Delay-in, 11.
36...Comparator, S7...And gate. Pin applicant: Canon Co., Ltd.

Claims (1)

[Claims] 1) The gray scale representation of the m image is expressed as a binary image signal V.
In an image signal binarization device that performs r-conversion. 1. A black level peak hold means for holding the peak value of the black level of the image (PI), a white level peak hold means for holding the peak value of the own level of the image signal, and an output of the black level peak hold means. Set the level to B,
Also, the output level W of the white level peak hold means is
As a foot addition of b k k' or more and l or less. T=kB+(/-k)W The output value gT of the calculation means and 1w4 calculation means that performs the calculation
An apparatus for binarizing l# image signals, characterized in that it has a converting means for converting the 1 image 100 into a binarized signal using as a reference level. In an image decoding binarization device which converts an image into a binary image signal. Cocoon arrangement-Zeng! The black level beak bold means holds the peak value of the black level of the image signal #, and the black level beak bold means holds the peak value of the white level of the image signal No. subtracting means for calculating the difference between the output level of the output level and the output level of the white level peak hold means; a multiplication means for multiplying the output level of the 1lli subtraction means by a constant level; Level peak hold means level and [
and an addition means for adding. An image characterized by having a comparison means for obtaining a binary signal by measuring the magnitude of the m-image gsg and the contact with the m-image gsg using the #I4MJ calculation tD output as a reference level through a delay means. Signal binarization device. Illusion - image cDs? An image signal binarization device KW converts jk into a binary m image signal after multilevel quantizing the image signal into a digital I# image signal by analog-to-digital conversion, and converts it into a binary m image signal. A black level peak hold means that holds the peak value of the black level of the signal, a white level peak hold circuit that holds the peak value of the white level of the digital the signal, and an output level of the bell hold circuit and liU notation. a subtraction circuit that calculates the difference between the output level of the own level peak hold circuit; a multiplication circuit that increases the output level of the subtraction circuit by one level; and an output level of the multiplication circuit and the output level of the white level peak hold circuit. 27a arithmetic circuit that adds N, and the output of the adder circuit is set as a reference level, and the above-mentioned dental image signal is directly added to the large and small size sum through the Process III low circuit, and a comparison is made to obtain a binarized signal (b)