JPS58182835A - Treatment of substrate for thin film transistor - Google Patents
Treatment of substrate for thin film transistorInfo
- Publication number
- JPS58182835A JPS58182835A JP6580782A JP6580782A JPS58182835A JP S58182835 A JPS58182835 A JP S58182835A JP 6580782 A JP6580782 A JP 6580782A JP 6580782 A JP6580782 A JP 6580782A JP S58182835 A JPS58182835 A JP S58182835A
- Authority
- JP
- Japan
- Prior art keywords
- grain boundary
- diffused
- atoms
- substrate
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 238000005204 segregation Methods 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- 238000005224 laser annealing Methods 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract description 2
- 229910052734 helium Inorganic materials 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 125000004429 atom Chemical group 0.000 description 7
- 239000010410 layer Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 238000003672 processing method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005324 grain boundary diffusion Methods 0.000 description 2
- 239000011856 silicon-based particle Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は多結晶材料の表面の結晶粒界に材料の原子とは
異る原子半径をもつ原子を拡散させた後、−回収上のア
ニールを行い、前記二種類の原子とは異った原子を多結
晶材料中に拡散させ、結晶粒界の電気特性を改善し、移
動度の高い薄膜トランジスタを得るための半導体基板の
処理方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention involves diffusing atoms having an atomic radius different from that of the material into the grain boundaries on the surface of a polycrystalline material, and then performing annealing for recovery. The present invention relates to a semiconductor substrate processing method for diffusing atoms different from the above two types of atoms into a polycrystalline material to improve the electrical properties of grain boundaries and obtain a thin film transistor with high mobility.
従来多結晶を用いた電気装置は電解コンデンサ、セラミ
ックコンデンサ、抵抗器など受動素子に多いが能動素子
にはあまり見当らない。半導体セラミックスコンデンサ
に於ては、結晶粒界に沿って異種原子を拡散させて絶縁
層とし、誘導率の大きいコンデンサをつくったり、実効
誘電体厚みの小さなコンデンサをつくったりしている。Conventional electrical devices using polycrystals are often found in passive devices such as electrolytic capacitors, ceramic capacitors, and resistors, but they are rarely found in active devices. In semiconductor ceramic capacitors, different atoms are diffused along the grain boundaries to form an insulating layer to create capacitors with high dielectric constant or with small effective dielectric thickness.
不純物は粒界及びバルク結晶にも拡散し、粒界偏析の効
果は少い。また特に結晶粒径を大きく成長させるという
ことはなく、これをツー
用いて作製した薄膜トランジスタの特性は嵐＜。Impurities also diffuse into grain boundaries and bulk crystals, and the effect of grain boundary segregation is small. In addition, the crystal grain size is not particularly grown to a large size, and the characteristics of thin film transistors fabricated using this method are as good as Arashi.
電界効果移動度は多結晶８１基−片〜２−／ｖ・濃であ
る。The field effect mobility is between 81 polycrystalline groups and 2-/v.concentration.
本発明の目的は結晶粒界に多結晶材料とは異る原子を拡
散させ、アニールを行うことによって、従来にない粒径
の大きな半導体材料を得、これを用いて作製した薄膜ト
ランジスタの電界効果移動度が８０〜１２０ｄ／Ｖｓｅ
ｃにも達するための多結晶半導体基板の処理方法を提供
するにある。The purpose of the present invention is to diffuse atoms different from those in polycrystalline materials into the grain boundaries and perform annealing to obtain a semiconductor material with an unprecedentedly large grain size, and to achieve field-effect migration of thin film transistors fabricated using this material. Degree is 80-120d/Vse
An object of the present invention is to provide a method for processing a polycrystalline semiconductor substrate so as to reach even the highest temperature.
本発明は、例えば基板としてＳｌ ウニ％−、ガラス
等が選ばれ、この上に多結晶シリコンが減圧ＣＶＤ法に
よって堆積される。この基板に、キャリアガスとともに
水素、ヘリウム、酸素等を高温（例えば６００℃）で送
り、粒界偏析させる。これをレーザー、電子線、熱、な
どでアニールし、後に不純物原子としてＰ、 Ｂ、 Ａ
８ などをイオン注入する。イオン注入後加熱しても
よい。In the present invention, for example, a substrate such as Sl, glass, or the like is selected, and polycrystalline silicon is deposited thereon by a low pressure CVD method. Hydrogen, helium, oxygen, etc. are sent to this substrate together with a carrier gas at a high temperature (for example, 600° C.) to cause grain boundary segregation. This is annealed using laser, electron beam, heat, etc., and later P, B, and A are formed as impurity atoms.
8 etc. is ion-implanted. Heating may be performed after ion implantation.
本発明によると、多結晶シリコンの粒子が１０μｍ以上
にも成長し、これを用いて作製した薄膜トランジスタの
電界効果移動度が１２０ｉ ／ Ｖ・冠にもなりうる。According to the present invention, polycrystalline silicon particles grow to a size of 10 μm or more, and the field effect mobility of a thin film transistor manufactured using the polycrystalline silicon particles can be as high as 120 i/V·cap.
第１図は基板の上に堆積された多結晶シリコンの断面を
示す。ｌは結晶粒、２は粒界拡散層、３は未拡散の粒界
である。４はバルク多結晶の拡散層である。このように
多結晶とは異る原子半径をもつ原子例えばＨ２、Ｈｅ
、 Ｏ等を表層部から拡散させると粒界では内部にまで
拡散し、粒界の電気特性を変化させる。一方粒子の成長
はレーザーアニール等で行われ、結晶成長は素子の移動
度の向上につながる。この基板を用いると第２図で示さ
れたように互に絶縁されたＭＯ８Ｉ−ランジスタが製作
可能である。２１はＰ型Ｓｌ 薄膜母体、２２は酸素
を拡散した粒界領域、２３は酸素の拡散していない粒界
領域、２４はｎ型拡散領域、２５はガラス又はセラミッ
クス基板、２６はＳｉＯ，蒸着膜、２７はゲート電極で
ある。レーザーアニールのレーザー出力はＩＯＷ、処理
後の多結晶シリコンの平均粒径は１０μｍ１素子の電界
効果移動度は１２０ｃｊ／Ｖ・気にも適した。FIG. 1 shows a cross section of polycrystalline silicon deposited on a substrate. 1 is a crystal grain, 2 is a grain boundary diffusion layer, and 3 is an undiffused grain boundary. 4 is a bulk polycrystalline diffusion layer. In this way, atoms with different atomic radii from polycrystals, such as H2, He
When , O, etc. are diffused from the surface layer, they diffuse inside the grain boundaries, changing the electrical characteristics of the grain boundaries. On the other hand, particle growth is performed by laser annealing or the like, and crystal growth leads to improved device mobility. Using this substrate, it is possible to produce mutually insulated MO8I transistors as shown in FIG. 21 is a P-type Sl thin film matrix, 22 is a grain boundary region where oxygen is diffused, 23 is a grain boundary region where oxygen is not diffused, 24 is an n-type diffusion region, 25 is a glass or ceramic substrate, and 26 is a SiO, vapor deposited film. , 27 are gate electrodes. The laser output for laser annealing was IOW, and the average grain size of polycrystalline silicon after treatment was 10 μm, and the field effect mobility of one element was 120 cj/V.
以上示したように本発明製造法によれば粒界偏析と拡散
、粒子成長を同時に行い、多結晶材料の電気特性を着る
しく改善できるので工業的にすぐれた半導体基板処理方
法ということができる。As shown above, according to the manufacturing method of the present invention, grain boundary segregation, diffusion, and grain growth can be performed simultaneously, and the electrical properties of polycrystalline materials can be significantly improved, so that it can be said to be an industrially excellent semiconductor substrate processing method.
第１図は本発明の一実施例の基板処理方法を説明するた
めの図、第２図はその処理基板を用いた素子の一例を示
す図である。
１・・・結晶粒、２・・・粒界拡散層、３・・・未拡散
粒界、４・・・バルク多結晶拡散層。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図FIG. 1 is a diagram for explaining a substrate processing method according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a device using the processed substrate. DESCRIPTION OF SYMBOLS 1... Crystal grain, 2... Grain boundary diffusion layer, 3... Undiffused grain boundary, 4... Bulk polycrystalline diffusion layer. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2
Claims (1)
原子半径の原子を拡散させた後、−回収上のアニールを
行い、＠起重種類の原子とは異った不純物原子を多結晶
材料中に拡散させることを特徴とする薄膜トランジスタ
用基板の処理方法。After diffusing atoms with an atomic radius different from the atoms of the material into the grain boundaries on the surface of the polycrystalline material, annealing is performed to collect impurity atoms different from the type of atoms of the A method for processing a substrate for a thin film transistor, characterized by diffusing it into a polycrystalline material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6580782A JPS58182835A (en) | 1982-04-20 | 1982-04-20 | Treatment of substrate for thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6580782A JPS58182835A (en) | 1982-04-20 | 1982-04-20 | Treatment of substrate for thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58182835A true JPS58182835A (en) | 1983-10-25 |
Family
ID=13297662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6580782A Pending JPS58182835A (en) | 1982-04-20 | 1982-04-20 | Treatment of substrate for thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182835A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943837A (en) * | 1987-03-11 | 1990-07-24 | Hitachi, Ltd. | Thin film semiconductor device and method of fabricating the same |
| US5035488A (en) * | 1987-06-12 | 1991-07-30 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing liquid crystal devices having semiconductor switching elements |
-
1982
- 1982-04-20 JP JP6580782A patent/JPS58182835A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943837A (en) * | 1987-03-11 | 1990-07-24 | Hitachi, Ltd. | Thin film semiconductor device and method of fabricating the same |
| US5035488A (en) * | 1987-06-12 | 1991-07-30 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing liquid crystal devices having semiconductor switching elements |
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