JPS5816564U

JPS5816564U - hysteresis circuit

Info

Publication number: JPS5816564U
Application number: JP10859981U
Authority: JP
Inventors: 長沢　利紀
Original assignee: 株式会社チノ−
Priority date: 1981-07-23
Filing date: 1981-07-23
Publication date: 1983-02-01

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第２図は、この考案の一実施例を示す構成説明図、第１
図、第３図、第４図、第５図、第６図、第７図はそれぞ
れ動作説明図である。２１．２２・・・・・・比較器、３・・・・・・アンド
回路、４・・・・・・ノア回路、５・・・・・・Ｒ−Ｓ
フリップフロップ回路。FIG. 2 is a configuration explanatory diagram showing one embodiment of this invention;
, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are operation explanatory diagrams, respectively. 21.22...Comparator, 3...AND circuit, 4...NOR circuit, 5...R-S
flip-flop circuit.

Claims

[Scope of utility model registration request]

a first comparator that produces a predetermined output signal when the input signal is greater than a first set value; and a second comparator that produces a predetermined output signal when the input signal is greater than a second set value. A comparator, an AND circuit that takes the AND of the surface outputs of the first and second comparators, a NOR circuit that takes the AND of the surface outputs of the first and second comparators, and the AND circuit output goes to the S terminal. At the same time, the NOR circuit output is supplied to the R terminal, or the AND circuit output is supplied to the R terminal, and the NOR circuit output is supplied to the S terminal, and the output is taken out from the Q terminal or the Q terminal.
A hysteresis circuit that is equipped with an S flip-flop circuit and takes out a hysteresis output.