JPS58125881A - Constitution of vertical type resistance circuit - Google Patents
Constitution of vertical type resistance circuitInfo
- Publication number
- JPS58125881A JPS58125881A JP57007618A JP761882A JPS58125881A JP S58125881 A JPS58125881 A JP S58125881A JP 57007618 A JP57007618 A JP 57007618A JP 761882 A JP761882 A JP 761882A JP S58125881 A JPS58125881 A JP S58125881A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- film
- lower electrode
- resistance
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 229910052787 antimony Inorganic materials 0.000 claims abstract description 3
- 239000002887 superconductor Substances 0.000 claims description 6
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 14
- 230000004888 barrier function Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 229910001020 Au alloy Inorganic materials 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910016345 CuSb Inorganic materials 0.000 abstract 1
- 229910052732 germanium Inorganic materials 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- ZFTFAPZRGNKQPU-UHFFFAOYSA-N dicarbonic acid Chemical compound OC(=O)OC(O)=O ZFTFAPZRGNKQPU-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
- H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は二つの超電導電極間に抵抗薄膜をはさみ込むこ
とにより実現される縦型抵抗回路の構成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for configuring a vertical resistance circuit realized by sandwiching a resistance thin film between two superconducting electrodes.
従来、ジョセフソン素子集積回路には抵抗体が重要な回
路素子として用いられてきている。第1図はその最も基
本的な回路図を示すもので、ジ冒セフソン素子と抵抗体
が並列につながれている。Conventionally, resistors have been used as important circuit elements in Josephson element integrated circuits. Figure 1 shows the most basic circuit diagram, in which a diode Sefson element and a resistor are connected in parallel.
豪雑な回路であってもそのほとんどは、第1図の回路を
組合せて構成されたものである。第1図の回路を用いて
構成するジョセフソン集積回路では、二つの超電導体薄
膜間に酸化膜を介在させたトンネル型ジ曽セフソン接合
素子が用いられ、各電極と抵抗体薄膜をつなぐことによ
り第1図の回路を実現している。第2図にその一例を示
す。第2図に示すように抵抗回路部分は、抵抗部分と各
超電導電極との接続を行なう部分よりなる。図中におい
て、電流は矢印で示す方向に流れる。今この矢印方向の
抵抗の長さをlとして、lに対する抵抗値Hの変化を調
べると、第3図に示すようにl=0の極限においてもR
は零でない値FL。(〉0)を持つ。これは各超電導体
薄膜と抵抗体の接続部分において発生する接触抵抗であ
る。一般にこの値R0は、Hに比べて十分に小さいこと
が望ましく、そのためには接続面積を大きく取ることが
必要である。実際上このために、接続部分の面積と実質
の抵抗部分の面積が同程度となることもあり。Most of the complicated circuits are constructed by combining the circuits shown in FIG. In the Josephson integrated circuit constructed using the circuit shown in Figure 1, a tunnel-type Jiso-Sefson junction element is used, in which an oxide film is interposed between two superconducting thin films, and each electrode is connected to a resistive thin film. The circuit shown in Figure 1 is realized. An example is shown in FIG. As shown in FIG. 2, the resistive circuit portion consists of a portion that connects the resistive portion and each superconducting electrode. In the figure, current flows in the direction indicated by the arrow. Letting the length of the resistance in the direction of the arrow be l, if we examine the change in the resistance value H with respect to l, as shown in Figure 3, even in the limit of l = 0, R
is a non-zero value FL. It has (>0). This is the contact resistance generated at the connection between each superconductor thin film and the resistor. Generally, it is desirable that this value R0 is sufficiently smaller than H, and for this purpose it is necessary to provide a large connection area. In practice, for this reason, the area of the connection portion and the area of the actual resistance portion may be approximately the same.
集積化の点で大きな障害となっている。従来この問題を
解決する方法としては、第4図に示すように抵抗体なジ
曹セフソン素子の接合部分の真下に配置する方法が提案
されている。しカルこのような構造を用いた場合、最も
代表的でかつ実用性のある。Pb合金膜電極とAu1n
、抵抗体の回路では、Inの拡散現象により抵抗体と下
部電極の厚さのみを隔て存在するトンネル障壁層が経時
変化を受けるという実用上大きな問題がある。This is a major obstacle in terms of integration. Conventionally, as a method to solve this problem, a method has been proposed in which a dicarbonate Sefson element, which is a resistor, is placed directly below the joint portion, as shown in FIG. When this type of structure is used, it is the most representative and practical. Pb alloy film electrode and Au1n
In a circuit using a resistor, there is a big practical problem in that the tunnel barrier layer, which exists only by the thickness of the resistor and the lower electrode, changes over time due to the diffusion phenomenon of In.
本発明は、ジ冒セフソン集積回路において、ジ冒セフソ
ン素子に悪影響を及ぼすことなく、抵抗体と超電導体の
接続部分における接触抵抗を小さくするために生じる集
積化に対する障害を取り除くことを可能とする薄膜抵抗
回路の構成方法を提供することを目的としている。The present invention makes it possible to eliminate obstacles to integration that occur in order to reduce the contact resistance at the connection portion between a resistor and a superconductor in an integrated circuit without adversely affecting the integrated circuit elements. The purpose of this invention is to provide a method for configuring a thin film resistor circuit.
本発明では、抵抗体を二つの超電導体薄膜間にはさみ込
むことで、実質の抵抗部分と二つの接続部分を膜厚方向
に立体的に配置させ、接続のために余分な領域を必要と
しない、ジ冒セフソン集積回路用抵抗回路の構成を行な
うことが基本となっている。In the present invention, by sandwiching the resistor between two superconducting thin films, the actual resistance part and the two connection parts are arranged three-dimensionally in the film thickness direction, and no extra area is required for connection. The basic idea is to construct a resistor circuit for an integrated circuit.
以下、本発明の一実施例を第5図により説明する。第5
図(A)において、例えば、シリコン或いはガラス基板
9上にリフト・オフ法を用いるためのフィトレジストと
して例えばシブレイ社製AZ1350Jポジティブレジ
スト膜10を例えば厚さl〔μm〕程度に塗布(尚、以
下の工程で用いる)すト・レジストも同様な種類のもの
を用いる)した後1通常のリソグラフィー技術を適用し
てフィトレジスト膜IOのパターニングを行ない、一部
にレジスト膜開口部を設ける。次に第5図(B)に示す
工程においてジ、セフソン素子の下部電極を構成する例
えば、Pb、 In、 Au 合金などの蒸着を行な
う。次いで第5図(C)の工程において上記基板9を例
えばアセトン中に浸漬させフィトレジスト膜lOおよび
レジスト膜上に付着した蒸着膜を除去して下部電極3を
形成する。従来の抵抗体回路を含むジ冒セフソン回路で
は、先に第2図、第4図で示したように、下部電極の形
成に先立って抵抗体の形成を行なっておく必要があるが
、本発明によれば1本実施例に示すように先に下部電極
の形成を行なうことも可能である。次に第5図(D)で
示す工程において、第5図(A)から(C)と同様なリ
フトオフの手法により、例えばAu I n ! 。An embodiment of the present invention will be described below with reference to FIG. Fifth
In Figure (A), for example, an AZ1350J positive resist film 10 manufactured by Sibley Co., Ltd. is coated as a phytoresist for using a lift-off method on a silicon or glass substrate 9 to a thickness of about 1 [μm] (hereinafter referred to as phytoresist). (The same type of phytoresist is used in the step of 1) After that, the phytoresist film IO is patterned by applying a normal lithography technique, and openings in the resist film are formed in some parts. Next, in the step shown in FIG. 5(B), an alloy of Pb, In, Au, etc., which constitutes the lower electrode of the di-Sephson element, is vapor-deposited. Next, in the step of FIG. 5(C), the substrate 9 is immersed in, for example, acetone to remove the phytoresist film IO and the vapor deposited film deposited on the resist film, thereby forming the lower electrode 3. In the conventional circuit including a resistor circuit, as shown in FIGS. 2 and 4, it is necessary to form the resistor before forming the lower electrode, but the present invention According to 1, it is also possible to form the lower electrode first as shown in this embodiment. Next, in the step shown in FIG. 5(D), for example, Au I n! .
AuCr、 Curb、 CuA/ もしくはそれら
の複合体、あるいはBi、 Sb、 Te、 G・など
の半金属・半導体もしくはそれらの化合物などの蒸着に
より、下部電極上に抵抗体を形成する。尚抵抗膜の蒸着
を行なう直前に、抵抗体との接続を行なう下部電極表面
に、例えば、アルゴン、酸素などをエツチング・ガスと
するプラズマ・工、チング方法によりエツチングを施こ
すことで、接触抵抗を低減させかつ一定のものとするこ
とができる。続いて第5図(E)に示す工程において、
第5図(A)から(C)と同様なリフトオフの手法によ
り、例えばSiOなどの蒸着により、下部電極3表面と
抵抗体6上部に開口部を時つ層間絶縁膜層8を形成する
。次いで第5図(F)の工程において、第5図(A)の
工程と同様にしてジ璽セフソン素子の上部電極のための
レジスト膜上を形成した後、例えばアルゴン。A resistor is formed on the lower electrode by vapor deposition of AuCr, Curb, CuA/ or a composite thereof, or a semimetal/semiconductor such as Bi, Sb, Te, G, or a compound thereof. Immediately before vapor deposition of the resistive film, the contact resistance can be reduced by etching the surface of the lower electrode that will be connected to the resistor using a plasma etching method using etching gas such as argon or oxygen. can be reduced and kept constant. Subsequently, in the step shown in FIG. 5(E),
Using a lift-off method similar to that shown in FIGS. 5A to 5C, an interlayer insulating film layer 8 with openings formed on the surface of the lower electrode 3 and the upper part of the resistor 6 is formed by vapor deposition of, for example, SiO. Next, in the step of FIG. 5(F), after forming a resist film for the upper electrode of the diagonal Sefson element in the same manner as the step of FIG. 5(A), for example, argon gas is applied.
酸素などのエツチングガスによりSiO層間絶縁層8開
口部に露出した下部電極表面および抵抗体上部をプラズ
マ・工、チングして清浄化し、続けて下部電極3の露出
部分を熱酸化法あるいはプラズマ酸化法などにより酸化
させてトンネル障壁層の形成を行なう。次に第5図(G
)の工程において、第5図(B)ないしくC)と同様の
工程により例えば、Pb、Au合金あるいはPb、Bi
合金膜の上部電極5を形成すれば、トンネル型ジ、セフ
ソン素子と抵抗体を並列につないだ回路が完成する。The surface of the lower electrode and the upper part of the resistor exposed in the opening of the SiO interlayer insulating layer 8 are cleaned by plasma etching using an etching gas such as oxygen, and then the exposed portion of the lower electrode 3 is cleaned using a thermal oxidation method or a plasma oxidation method. A tunnel barrier layer is formed by oxidizing the material by, for example, Next, Figure 5 (G
), for example, Pb, Au alloy or Pb, Bi
By forming the upper electrode 5 of the alloy film, a circuit is completed in which the tunnel type diode and Sefson element and the resistor are connected in parallel.
本実施例によれば、ジ曽セフソン素子の二つの電極間に
抵抗体をはさみ込むことにより、実質の抵抗部分と接続
部分が立体的に配置され、抵抗体の集積化が図られてい
る。またこれをジョセフソン素子の接合部分から適当な
距離を隔てることにより、抵抗体が、拡散現象によりト
ンネル障壁層を経時変化させることを防止することも可
能であ本発明によれば、二つの超電導体層間に抵抗体を
はさみ込むことにより、実質の抵抗部分とその両端にお
ける接触部分を立体配置させることができるので、接触
部分に余分な面積を必要としないという抵抗体の集積化
を図る上での大きな効果がある。またこの構成方法は、
抵抗体を二つの超電導体層にはさみ込むことが要件であ
り、その超電導体層には任意の二つを選ぶことが可能で
ある。According to this embodiment, by sandwiching the resistor between the two electrodes of the Jiso-Sefson element, the actual resistance portion and the connection portion are arranged three-dimensionally, and the resistor is integrated. Furthermore, by separating the resistor from the junction part of the Josephson element by an appropriate distance, it is possible to prevent the resistor from changing the tunnel barrier layer over time due to diffusion phenomena. By sandwiching the resistor between body layers, the actual resistor part and the contact parts at both ends can be arranged three-dimensionally, which makes it possible to integrate the resistor without requiring extra area for the contact part. It has a big effect. Also, this configuration method is
The requirement is to sandwich the resistor between two superconductor layers, and any two superconductor layers can be selected.
従って回路構成上の自由度を増すという効果もある0Therefore, it has the effect of increasing the degree of freedom in circuit configuration.
第1図はジョセフソン素子と抵抗体を含む回路図、第2
図はジョセフソン素子と抵抗体を含む回路の斜視図、第
3喝は抵抗長と抵抗値の関係を示すグラフ、第4図はジ
ョセフソン素子と抵抗体を含む回路の要部断面図、第5
図(A)〜(G)は本発明一実施例における縦型抵抗回
路の製造工程を示す要部断面図である。
l・・・・・・ジ■セフソン素子、2・・・・・・抵抗
体、3・・・・・・ジ冒セフソノ素子の下部電極、4・
・・・・・同トンネル障壁層、5・・・・・・同上部電
極、6・・・・・・抵抗部分、7・・・・・・接触抵抗
部分、8・・・・・・層間絶縁層、9・・・・・・基板
、10・・・・・・レジスト膜、11・・・・・・蒸着
膜。Figure 1 is a circuit diagram including a Josephson element and a resistor;
The figure is a perspective view of a circuit including a Josephson element and a resistor, the third figure is a graph showing the relationship between resistance length and resistance value, the fourth figure is a sectional view of the main part of a circuit including a Josephson element and a resistor, and the third figure is a graph showing the relationship between resistance length and resistance value. 5
Figures (A) to (G) are sectional views of main parts showing the manufacturing process of a vertical resistance circuit according to an embodiment of the present invention. 1... Di-Sefson element, 2... Resistor, 3... Lower electrode of the D-Sefson element, 4...
...Tunnel barrier layer, 5...Top electrode, 6...Resistance part, 7...Contact resistance part, 8...Interlayer Insulating layer, 9... substrate, 10... resist film, 11... vapor deposited film.
Claims (1)
かあるいは、電極膜の片方もしくは両方を他の超電導体
層に置き換えて、該抵抗体を二つの超電導体によっては
さみ込むことにより抵抗体とその両端の接続部分を立体
配置させることにより抵抗体を流れる電流路をその膜厚
方向にとることを特徴とする縦型抵抗回路の構成方法。 26 前記薄膜抵抗体の材料としてAuIn2.Au
Cr。 Curb、CuA/もしくはそれらの複合体、あるいは
Bi、 Sb、Te、Si、Goなどの半金属・半導体
もしくはそれらの化合物を用いることを特徴とする特許
請求の範囲第1項記載のI縦型抵抗回路の構成方法。[Claims] 1. A thin film resistor is sandwiched between both electrodes of a Girocefson element, or one or both of the electrode films is replaced with another superconductor layer, and the resistor is sandwiched between two superconductors. A method for configuring a vertical resistance circuit, characterized in that the resistor and the connection portions at both ends thereof are arranged three-dimensionally so that the current path flowing through the resistor is in the direction of its film thickness. 26 AuIn2.2 as the material of the thin film resistor. Au
Cr. The I vertical resistor according to claim 1, characterized in that Curb, CuA/or a composite thereof, or a semimetal/semiconductor such as Bi, Sb, Te, Si, Go, or a compound thereof is used. How to configure a circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57007618A JPS58125881A (en) | 1982-01-22 | 1982-01-22 | Constitution of vertical type resistance circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57007618A JPS58125881A (en) | 1982-01-22 | 1982-01-22 | Constitution of vertical type resistance circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58125881A true JPS58125881A (en) | 1983-07-27 |
Family
ID=11670795
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57007618A Pending JPS58125881A (en) | 1982-01-22 | 1982-01-22 | Constitution of vertical type resistance circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58125881A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6221283A (en) * | 1985-07-19 | 1987-01-29 | Nippon Telegr & Teleph Corp <Ntt> | Superconductive integrated circuit |
MD174Z (en) * | 2009-05-19 | 2010-10-31 | Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы | Semiconducting material |
MD323Z (en) * | 2009-12-29 | 2011-08-31 | Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы | Thermoelectric microwire in glass insulation |
-
1982
- 1982-01-22 JP JP57007618A patent/JPS58125881A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6221283A (en) * | 1985-07-19 | 1987-01-29 | Nippon Telegr & Teleph Corp <Ntt> | Superconductive integrated circuit |
MD174Z (en) * | 2009-05-19 | 2010-10-31 | Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы | Semiconducting material |
MD323Z (en) * | 2009-12-29 | 2011-08-31 | Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы | Thermoelectric microwire in glass insulation |
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