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JPS58102569A - Manufacture of amorphous silicon solar battery - Google Patents

Manufacture of amorphous silicon solar battery

Info

Publication number
JPS58102569A
JPS58102569A JP56201288A JP20128881A JPS58102569A JP S58102569 A JPS58102569 A JP S58102569A JP 56201288 A JP56201288 A JP 56201288A JP 20128881 A JP20128881 A JP 20128881A JP S58102569 A JPS58102569 A JP S58102569A
Authority
JP
Japan
Prior art keywords
amorphous silicon
substrate
substrates
film
silicon solar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56201288A
Other languages
Japanese (ja)
Inventor
Kuniharu Yamada
邦晴 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56201288A priority Critical patent/JPS58102569A/en
Publication of JPS58102569A publication Critical patent/JPS58102569A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To facilitate the attachment and detachment of sample substrates and to improve the operability, by pushing the side surfaces of the substrates by springs when an amorphous silicon layer is formed so as to fix the substrates, and forming a film with a part of the upper surface being masked. CONSTITUTION:A pattern of a transparent electrode 42 is formed on the glass substrate 41, a part of the transparent electrode pattern is masked, and the amorphous silicon layer is formed. In setting the substrate when the amorphous silicon film is formed, the sample substrates 51, the pushing springs 52, and the stainless mask 53 are used. The sample substrates are deeply mounted with a substrate holder itself as a stopper. The side surfaces of the substrates are pushed by the springs, and the substrates are fixed. Thereafter the lead sides of the electrode are masked and a film is formed.

Description

【発明の詳細な説明】 本発明はアモルファスシリコン太陽電池の製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an amorphous silicon solar cell.

本発明の目的は操作性が優れ蓋産性の高いアモルファス
シリコン太陽電池の製造方法を提供することである。
An object of the present invention is to provide a method for manufacturing an amorphous silicon solar cell with excellent operability and high lid productivity.

モノシラン(sin、)あるいは四7ツ化硅素(si7
.)をプラズマ分解して得られる7モル7アスシリコン
は太陽光に対する光吸収係数が大である。光伝導度が高
い。基板の自由廣が大である等の理由から低価格太陽電
池の有望材料として注目を集めている。
Monosilane (sin) or silicon tetratride (si7)
.. ) has a large light absorption coefficient for sunlight. High photoconductivity. It is attracting attention as a promising material for low-cost solar cells because of the large free width of the substrate.

その主たる製造方法は真空槽内に所定のガスを導入して
所定の内圧とし、該真空槽内におけるグロー放電により
膜形成を行なうプラズマovn法である。
The main manufacturing method is a plasma ovn method in which a predetermined gas is introduced into a vacuum chamber to maintain a predetermined internal pressure, and a film is formed by glow discharge within the vacuum chamber.

第1図にプラズマOVD装置の概要を示す。Figure 1 shows an overview of the plasma OVD apparatus.

図において1.2.3は各々モノシラン、ホスフィン、
ジボランであり各ガスとも水素ガスで希釈している。4
,5.6はマスクローコントローラでガス流量の精密制
御を行なう。7は真空槽、8はンヤワーで高周波の一方
の電極を兼用している。
In the figure, 1.2.3 are monosilane, phosphine,
Diborane and each gas is diluted with hydrogen gas. 4
, 5.6 performs precise control of the gas flow rate using a mask row controller. 7 is a vacuum chamber, and 8 is a vacuum chamber which also serves as one of the high frequency electrodes.

9はサセプタ、10は基板加熱ヒータ、11は高周波電
源(通常1 i 56 M Hz )、12は試料基板
である。16は排気口で真空ポンプ系に接続されている
9 is a susceptor, 10 is a substrate heater, 11 is a high frequency power source (usually 1 i 56 MHz), and 12 is a sample substrate. 16 is an exhaust port connected to a vacuum pump system.

排気口13により真空排気を行ないながらマス70−コ
ントローラ4によりモノシランガスを導入し所定の内圧
(01〜5Torr)とした後、高周波電源1またより
電力を供給すると、電&I8とサセプタ9との間でグロ
ー放電を起こしプラズマを発生する。このグロー放電に
よりモノシランが分解され、試料基板12の表面にアモ
ルファスシリコン膜が形成される。
While performing vacuum evacuation through the exhaust port 13, monosilane gas is introduced through the mass 70-controller 4 to achieve a predetermined internal pressure (01 to 5 Torr), and then power is supplied from the high frequency power source 1 or the susceptor 9. Causes glow discharge and generates plasma. Monosilane is decomposed by this glow discharge, and an amorphous silicon film is formed on the surface of the sample substrate 12.

なお試料基板としてはガラス、金属(ステンレス、モリ
ブデン等)、高分子フィルム等が使用される。
Note that glass, metal (stainless steel, molybdenum, etc.), polymer film, etc. are used as the sample substrate.

該アモルファスシリコン膜に不純物ドープを行なう場合
、モノシランガスと同時にマス70−コントローラ5又
は6によりホスフィン又はジボランを流す、前者の場合
N形アモルファスシリコン膜が形成され、後者の場合P
形アモルファスンリコン膜が形成される。なおホスフィ
ンの代わりにアルシン(A−aH3)を用いても同様で
ある。
When doping the amorphous silicon film with impurities, phosphine or diborane is flowed through the mass 70 and the controller 5 or 6 at the same time as the monosilane gas. In the former case, an N-type amorphous silicon film is formed, and in the latter case, a P
An amorphous silicon film is formed. Note that the same effect can be obtained even if arsine (A-aH3) is used instead of phosphine.

希釈ガスとして水素、ヘリウム、アルゴン等が−用いら
れているが、特に水素が多用されている。
Hydrogen, helium, argon, etc. are used as the diluent gas, and hydrogen is particularly frequently used.

これはアモルファスシリコンを形成する場合、シリコン
原子のダングリングボンドを水素が補償し局在準位密度
を減少させるためである。
This is because when amorphous silicon is formed, hydrogen compensates for dangling bonds of silicon atoms and reduces the localized level density.

従来該アモルファスシリコン層形成時には基板ホルダー
に試料基板を並べ上からマスクをセットする方法であっ
たが、試料基板のサイズがバラツキを有するため位置決
めが難しく歩留が低かった。
Conventionally, when forming the amorphous silicon layer, a sample substrate was arranged on a substrate holder, and a mask was set from above. However, since the size of the sample substrate varied, positioning was difficult and the yield was low.

本発明はかかる欠点を除去するもので基板のセット方法
を改善することにより操作性及び歩留を向上し量産性を
高めたものである。
The present invention eliminates such drawbacks and improves operability and yield by improving the method of setting substrates, thereby increasing mass productivity.

以下図面に基づき本発明について更に詳細に記述する。The present invention will be described in more detail below based on the drawings.

第2図はアモルファスシリコン太陽電池の断面図を示す
FIG. 2 shows a cross-sectional view of an amorphous silicon solar cell.

ここで21はガラス基板、22は下部電極(工T0 、
8 n O!等の透明電極)、25はP形アモルファス
シリコン層、24はノンドープJll(1層)、25は
N形アモルファスシリコン層、26は上部電極(At、
−Mi、Or等の金属電極)である。
Here, 21 is a glass substrate, 22 is a lower electrode (T0,
8 n O! 25 is a P-type amorphous silicon layer, 24 is a non-doped Jll (1 layer), 25 is an N-type amorphous silicon layer, 26 is an upper electrode (At,
-metal electrodes such as Mi and Or).

第3図は他のアモルファスシリコン太陽電池(7)断面
図である。
FIG. 3 is a sectional view of another amorphous silicon solar cell (7).

ここで31はガラス基板、32は上部電極(1丁0.8
nO,等の透明電極)、33はP形アモルファスシリコ
ンpd、54はノンドープ層(ill)、55はw形ア
モルファスシリコン層、56+i下部電極(At、Ni
  、Or等の金属電極)である。
Here, 31 is a glass substrate, 32 is an upper electrode (1 piece 0.8
33 is a p-type amorphous silicon pd, 54 is a non-doped layer (ill), 55 is a w-type amorphous silicon layer, 56+i lower electrode (At, Ni
, Or, etc.).

上記太陽電池はいずれも透明電極側から光が入射する。In all of the above solar cells, light enters from the transparent electrode side.

餉4図はアモルファスシリコン太陽電池の上面図である
Figure 4 is a top view of an amorphous silicon solar cell.

ここで41はガラス基板、42は下部電極、43はアモ
ルファスシリコン層(pstsn層)、46は上部電極
である。
Here, 41 is a glass substrate, 42 is a lower electrode, 43 is an amorphous silicon layer (pstsn layer), and 46 is an upper electrode.

ガラス基板41上に透明電極42のパターンを形成し該
透明電極パターンの一部をマスキングしアモルファスシ
リコン層を形成する。
A pattern of transparent electrodes 42 is formed on a glass substrate 41, and a part of the transparent electrode pattern is masked to form an amorphous silicon layer.

第5図は本発明に基づくアモルファスシリコン膜形成時
の基板のセット状況を示す上面図である。
FIG. 5 is a top view showing how a substrate is set during formation of an amorphous silicon film according to the present invention.

ここで51は試料基板、52は押えバネ、53はステン
レスマスクでアル。
Here, 51 is a sample substrate, 52 is a presser spring, and 53 is a stainless steel mask.

第6図は上記基板のセット状況の断面図を示す。FIG. 6 shows a sectional view of the setting state of the above-mentioned substrates.

ここで61は試料基板、62は押えバネ、63はステン
レスマスク、64°は基板ホルダーである。
Here, 61 is a sample substrate, 62 is a presser spring, 63 is a stainless steel mask, and 64° is a substrate holder.

試料基板は基板ホルダー自身をストッパーとして奥まで
入れ、基板側面をバネで押え基板の固定を行なう。その
後電極のリード側をマスキングして成膜を行かう。
Insert the sample substrate all the way into the chamber using the substrate holder itself as a stopper, and use springs to press the sides of the substrate to fix the substrate. After that, film formation is performed while masking the lead side of the electrode.

本発明の製造方法によれば試料基板の着脱が極めて容易
であり操作性が大巾に向上、する。
According to the manufacturing method of the present invention, it is extremely easy to attach and detach the sample substrate, and the operability is greatly improved.

又試料基板の側面を固定するためマスクとの位置ズレが
すく電極のシ目−ト等のトラブルが減少した。
Also, since the side surface of the sample substrate is fixed, there is less misalignment with the mask, reducing problems such as electrode seams.

なおここではステンレスマスクの場合を例にあげたがリ
ン青銅、ニッケル、モリブデン化合の金属マスクでも同
等の結果が得られている。
Although a stainless steel mask is used as an example here, similar results have been obtained with metal masks made of phosphor bronze, nickel, or molybdenum compounds.

以上詳述した如く本発明によれば操作性に優れ量産性の
高いアモルファスシリコン太陽電池の製造方法を提供す
るものであり、アモルファスゲルマニウム略他の非晶質
半導体デバイスの製造にも適用できる。
As described in detail above, the present invention provides a method for manufacturing amorphous silicon solar cells with excellent operability and high mass productivity, and can also be applied to manufacturing amorphous germanium and other amorphous semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はプラズマOVD装置の概要を示す。 第2図はアモルファスシリコン太陽電池の断面を示す。 第3図は他のアモルファスシリコン太陽1に池の断面を
示す。 第4図はアモルファスシリコン太陽電池の上面図を示す
。 5SviJは本発明に基づくアモルファスシリコン#形
成時の基板のセット状況を示す上面図。 第6WJは本発明に基づくアモ゛ル7アスシリコンII
形成時の基板のセット状況の断面図である。 第1図 第2図 第3図 第4図 第6図
FIG. 1 shows an outline of a plasma OVD apparatus. FIG. 2 shows a cross section of an amorphous silicon solar cell. FIG. 3 shows a cross section of another amorphous silicon solar cell 1. FIG. 4 shows a top view of an amorphous silicon solar cell. 5SviJ is a top view showing how the substrate is set during the formation of amorphous silicon # according to the present invention. The 6th WJ is Amol 7As silicon II based on the present invention.
FIG. 3 is a cross-sectional view of the setting state of the substrate during formation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に形成された下部電極上にPin構造のアモ
ルファスシリコン層を形成し、更に上部電極を形成して
よるアモルファスシリコン太陽電池において、該アモル
ファスシリコン層は真空排気系により減圧にし得る真空
槽内に所定のガス(モノシラン、ジボラン、ホスフィン
等)を導入して所定の内圧とし、該真空槽内における・
放電現象により成膜を行ない、該アモルファスシリコン
層形成時に基板側面をバネで押え基板の固定を行ない、
上面の一部をマスキングして成膜することを特徴とする
アモルファスシリコン太陽電池の製造方法。
In an amorphous silicon solar cell in which an amorphous silicon layer with a pin structure is formed on a lower electrode formed on an insulating substrate and an upper electrode is further formed, the amorphous silicon layer is placed in a vacuum chamber where the pressure can be reduced by an evacuation system. A predetermined gas (monosilane, diborane, phosphine, etc.) is introduced into the vacuum chamber to achieve a predetermined internal pressure.
The film is formed by a discharge phenomenon, and when forming the amorphous silicon layer, the substrate is fixed by pressing the side surface of the substrate with a spring,
A method for manufacturing an amorphous silicon solar cell, characterized by forming a film while masking a part of the upper surface.
JP56201288A 1981-12-14 1981-12-14 Manufacture of amorphous silicon solar battery Pending JPS58102569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56201288A JPS58102569A (en) 1981-12-14 1981-12-14 Manufacture of amorphous silicon solar battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56201288A JPS58102569A (en) 1981-12-14 1981-12-14 Manufacture of amorphous silicon solar battery

Publications (1)

Publication Number Publication Date
JPS58102569A true JPS58102569A (en) 1983-06-18

Family

ID=16438485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56201288A Pending JPS58102569A (en) 1981-12-14 1981-12-14 Manufacture of amorphous silicon solar battery

Country Status (1)

Country Link
JP (1) JPS58102569A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04296473A (en) * 1991-03-26 1992-10-20 Shin Etsu Polymer Co Ltd Heat seal connector
JPH06181076A (en) * 1992-03-12 1994-06-28 Shin Etsu Polymer Co Ltd Heat seal connector
JPH07122320A (en) * 1993-10-21 1995-05-12 Nec Corp Heat seal connector

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04296473A (en) * 1991-03-26 1992-10-20 Shin Etsu Polymer Co Ltd Heat seal connector
JPH06181076A (en) * 1992-03-12 1994-06-28 Shin Etsu Polymer Co Ltd Heat seal connector
JPH0817100B2 (en) * 1992-03-12 1996-02-21 信越ポリマー株式会社 Heat seal connector
JPH07122320A (en) * 1993-10-21 1995-05-12 Nec Corp Heat seal connector

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