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JPS5773952A - Chip for face down bonding and production thereof - Google Patents

Chip for face down bonding and production thereof

Info

Publication number
JPS5773952A
JPS5773952A JP55149404A JP14940480A JPS5773952A JP S5773952 A JPS5773952 A JP S5773952A JP 55149404 A JP55149404 A JP 55149404A JP 14940480 A JP14940480 A JP 14940480A JP S5773952 A JPS5773952 A JP S5773952A
Authority
JP
Japan
Prior art keywords
layer
conductive layer
mask
chip
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55149404A
Other languages
Japanese (ja)
Inventor
Toru Kawanobe
Keiji Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55149404A priority Critical patent/JPS5773952A/en
Publication of JPS5773952A publication Critical patent/JPS5773952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make a chip for wire bonding for common use and to reduce production costs by a method wherein a metal conductive layer which is corrosion resistant and to be connected to the pad part of a wiring layer is formed and extended to the desired region on a passivation film and a bump is provided on the conductive layer. CONSTITUTION:A passivation film 4 (prasma nitrified film) is piled on the whole surface of a wafer 2 where a circuit element and a wiring layer 1 have been formed, while an opening is made in a bonding pad part. Next a conductive layer 6 consisting of, for instance, a Ti layer 7, a Cu layer 8 and a Ti layer 9 is deposited in order by evaporation and then coated with polyimide resin. After this, a mask 10 in which a bump hole 11 and the unnecessary region of the conductive layer 6 have been etched is provided. Next the whole region excluding the hole 11 is covered with a photoresist mask 12 and the exposed Ti layer 9 is etched. Then an Ni layer 13, an Sn layer 14 and a Pb layer 15 are plated in order. Next after the resist mask 12 is removed toform a bump 16 by means of heat processing, the unnecessary conductive layer 6 and the mask layer 10 are removed in order by etching them. By so doing, it becomes unnecessary to pariticularly design a chip for facing down, thus reducing production costs.
JP55149404A 1980-10-27 1980-10-27 Chip for face down bonding and production thereof Pending JPS5773952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55149404A JPS5773952A (en) 1980-10-27 1980-10-27 Chip for face down bonding and production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55149404A JPS5773952A (en) 1980-10-27 1980-10-27 Chip for face down bonding and production thereof

Publications (1)

Publication Number Publication Date
JPS5773952A true JPS5773952A (en) 1982-05-08

Family

ID=15474384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55149404A Pending JPS5773952A (en) 1980-10-27 1980-10-27 Chip for face down bonding and production thereof

Country Status (1)

Country Link
JP (1) JPS5773952A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5046161A (en) * 1988-02-23 1991-09-03 Nec Corporation Flip chip type semiconductor device
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5892179A (en) * 1995-04-05 1999-04-06 Mcnc Solder bumps and structures for integrated redistribution routing conductors
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US7358174B2 (en) 2004-04-13 2008-04-15 Amkor Technology, Inc. Methods of forming solder bumps on exposed metal pads
US7495326B2 (en) 2002-10-22 2009-02-24 Unitive International Limited Stacked electronic structures including offset substrates
US8674494B2 (en) 2011-08-31 2014-03-18 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046161A (en) * 1988-02-23 1991-09-03 Nec Corporation Flip chip type semiconductor device
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5374893A (en) * 1992-03-04 1994-12-20 Mcnc Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5381946A (en) * 1992-03-04 1995-01-17 Mcnc Method of forming differing volume solder bumps
US6222279B1 (en) 1995-03-20 2001-04-24 Mcnc Solder bump fabrication methods and structures including a titanium barrier layer
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6392163B1 (en) 1995-04-04 2002-05-21 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps
US5892179A (en) * 1995-04-05 1999-04-06 Mcnc Solder bumps and structures for integrated redistribution routing conductors
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
US6389691B1 (en) 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US7495326B2 (en) 2002-10-22 2009-02-24 Unitive International Limited Stacked electronic structures including offset substrates
US7358174B2 (en) 2004-04-13 2008-04-15 Amkor Technology, Inc. Methods of forming solder bumps on exposed metal pads
US8674494B2 (en) 2011-08-31 2014-03-18 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same
US9412720B2 (en) 2011-08-31 2016-08-09 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same

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