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JPS573431A - Complementary mos logical circuit - Google Patents

Complementary mos logical circuit

Info

Publication number
JPS573431A
JPS573431A JP7637880A JP7637880A JPS573431A JP S573431 A JPS573431 A JP S573431A JP 7637880 A JP7637880 A JP 7637880A JP 7637880 A JP7637880 A JP 7637880A JP S573431 A JPS573431 A JP S573431A
Authority
JP
Japan
Prior art keywords
input signal
logical circuit
output terminal
complementary mos
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7637880A
Other languages
Japanese (ja)
Inventor
Makoto Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7637880A priority Critical patent/JPS573431A/en
Publication of JPS573431A publication Critical patent/JPS573431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:To establish a ternary logical circuit in which an inverting circuit can be omitted, by making the output state to a high impedance state with one kind of input signal. CONSTITUTION:When an input signal Q is ''0'', N-MOSs 23, 25 are turned off, a DC current path toward an output terminal 21 is interrupted and the output terminal 21 is at high impedance state. When an input signal Q is at ''1'' and an input signal A is ''0'', since P-MOS 22 and N-MOS 23 are both turned on, the output terminal 21 is at ''1'', and when the input signal A is at ''1'', since both the N-MOSs 23, 25 are turned on, the output terminal 21 is at ''0''.
JP7637880A 1980-06-06 1980-06-06 Complementary mos logical circuit Pending JPS573431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7637880A JPS573431A (en) 1980-06-06 1980-06-06 Complementary mos logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7637880A JPS573431A (en) 1980-06-06 1980-06-06 Complementary mos logical circuit

Publications (1)

Publication Number Publication Date
JPS573431A true JPS573431A (en) 1982-01-08

Family

ID=13603667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7637880A Pending JPS573431A (en) 1980-06-06 1980-06-06 Complementary mos logical circuit

Country Status (1)

Country Link
JP (1) JPS573431A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179914A (en) * 1989-12-08 1991-08-05 Nec Corp Bus driver circuit
JPH088722A (en) * 1995-07-10 1996-01-12 Hitachi Ltd Tree-state circuit
US5631579A (en) * 1994-11-21 1997-05-20 Mitsubishi Denki Kabushiki Kaisha Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages
US5811992A (en) * 1994-12-16 1998-09-22 Sun Microsystems, Inc. Dynamic clocked inverter latch with reduced charged leakage and reduced body effect

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179914A (en) * 1989-12-08 1991-08-05 Nec Corp Bus driver circuit
US5631579A (en) * 1994-11-21 1997-05-20 Mitsubishi Denki Kabushiki Kaisha Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages
US5811992A (en) * 1994-12-16 1998-09-22 Sun Microsystems, Inc. Dynamic clocked inverter latch with reduced charged leakage and reduced body effect
JPH088722A (en) * 1995-07-10 1996-01-12 Hitachi Ltd Tree-state circuit

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