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JPS5730489A - Time-division memory system - Google Patents

Time-division memory system

Info

Publication number
JPS5730489A
JPS5730489A JP10433680A JP10433680A JPS5730489A JP S5730489 A JPS5730489 A JP S5730489A JP 10433680 A JP10433680 A JP 10433680A JP 10433680 A JP10433680 A JP 10433680A JP S5730489 A JPS5730489 A JP S5730489A
Authority
JP
Japan
Prior art keywords
channel
data
memory
channels
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10433680A
Other languages
Japanese (ja)
Other versions
JPS6130799B2 (en
Inventor
Yoshiaki Sutani
Hisao Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10433680A priority Critical patent/JPS5730489A/en
Publication of JPS5730489A publication Critical patent/JPS5730489A/en
Publication of JPS6130799B2 publication Critical patent/JPS6130799B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To decrease the number of memories, and to simplify the control over transmission and reception which reducing the price of a channel device, by using part of a channel memory, included in the time-division switch of a digital switchboard, for no-channel data. CONSTITUTION:Data transferred from a multiplexer 2 in a circuit correspondence part 1 to a highway 4, having 15-frame multiframe constitution by assigning 120 channels of channel signals and 8 channels of no-channel signals to one frame, are transmitted over 120 channels each of the channel and no-channel signals. Each memory cycle of the channel memory 9 of a time-division switch 8 consists of four steps of sequential writing, random reading, no-channel data reading, and random reading. According to outputs of counters 11 and 21, data are written by being specified by an address selector and channel data read out by the address RRA of a holding memory are transferred to the next stage via a register 23. No-channel data are readout by a signal controller 14 and transferred to the device 14.
JP10433680A 1980-07-31 1980-07-31 Time-division memory system Granted JPS5730489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10433680A JPS5730489A (en) 1980-07-31 1980-07-31 Time-division memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10433680A JPS5730489A (en) 1980-07-31 1980-07-31 Time-division memory system

Publications (2)

Publication Number Publication Date
JPS5730489A true JPS5730489A (en) 1982-02-18
JPS6130799B2 JPS6130799B2 (en) 1986-07-16

Family

ID=14378084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10433680A Granted JPS5730489A (en) 1980-07-31 1980-07-31 Time-division memory system

Country Status (1)

Country Link
JP (1) JPS5730489A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856599A (en) * 1981-09-11 1983-04-04 ミテル・コ−ポレ−シヨン Time division switching matrix
JPS5979697A (en) * 1982-10-27 1984-05-08 Fujitsu Ltd Control method of channel memory
JPS63212294A (en) * 1987-01-23 1988-09-05 マイテル・コーポレーション Digital signal processing system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856599A (en) * 1981-09-11 1983-04-04 ミテル・コ−ポレ−シヨン Time division switching matrix
JPH0141078B2 (en) * 1981-09-11 1989-09-01 Mitel Corp
JPS5979697A (en) * 1982-10-27 1984-05-08 Fujitsu Ltd Control method of channel memory
JPH0139277B2 (en) * 1982-10-27 1989-08-18 Fujitsu Ltd
JPS63212294A (en) * 1987-01-23 1988-09-05 マイテル・コーポレーション Digital signal processing system
JPH0693797B2 (en) * 1987-01-23 1994-11-16 マイテル・コーポレーション Digital signal processing system

Also Published As

Publication number Publication date
JPS6130799B2 (en) 1986-07-16

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