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JPS57181144A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57181144A
JPS57181144A JP56066460A JP6646081A JPS57181144A JP S57181144 A JPS57181144 A JP S57181144A JP 56066460 A JP56066460 A JP 56066460A JP 6646081 A JP6646081 A JP 6646081A JP S57181144 A JPS57181144 A JP S57181144A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
semiconductor element
ceramic base
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56066460A
Other languages
Japanese (ja)
Inventor
Takeyumi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56066460A priority Critical patent/JPS57181144A/en
Publication of JPS57181144A publication Critical patent/JPS57181144A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To relieve thermal distortion and enhance integrity, by combining a ceramic base mounting a semiconductor element, and a resin printed circuit board forming a conductor pattern with a conductive stress absorber. CONSTITUTION:A conductor layer 12 on a ceramic base 10 mounting a semiconductor element 11 is connected to a conductor pattern 16 on a printed circuit board 15 of epoxy resin through a sectionally U-shaped stress absorber 14 of conductive material. This avoids the influence of thermal stress load, and yet improves the integrity.
JP56066460A 1981-05-01 1981-05-01 Semiconductor device Pending JPS57181144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56066460A JPS57181144A (en) 1981-05-01 1981-05-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56066460A JPS57181144A (en) 1981-05-01 1981-05-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57181144A true JPS57181144A (en) 1982-11-08

Family

ID=13316397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56066460A Pending JPS57181144A (en) 1981-05-01 1981-05-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57181144A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132099A (en) * 1984-07-24 1986-02-14 富士通株式会社 Power spectrum envelope extraction system
US4647126A (en) * 1985-06-17 1987-03-03 Sperry Corporation Compliant lead clip
US4682829A (en) * 1985-06-13 1987-07-28 Amp Incorporated Surface mount socket for dual in-line package
US4724472A (en) * 1983-02-17 1988-02-09 Fujitsu Limited Semiconductor device
US4739125A (en) * 1985-09-27 1988-04-19 Hitachi, Ltd. Electric component part having lead terminals
JPS63118262U (en) * 1987-01-23 1988-07-30
JPH0189752U (en) * 1988-12-08 1989-06-13
JPH0193745U (en) * 1987-12-16 1989-06-20
JPH07122833A (en) * 1993-10-26 1995-05-12 Nec Corp Integrated circuit package
JP2016025298A (en) * 2014-07-24 2016-02-08 セイコーエプソン株式会社 Electronic component, method of manufacturing electronic component, electronic apparatus, and mobile
JP2016139790A (en) * 2015-01-26 2016-08-04 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and mounting board thereof

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4724472A (en) * 1983-02-17 1988-02-09 Fujitsu Limited Semiconductor device
JPS6132099A (en) * 1984-07-24 1986-02-14 富士通株式会社 Power spectrum envelope extraction system
US4682829A (en) * 1985-06-13 1987-07-28 Amp Incorporated Surface mount socket for dual in-line package
US4647126A (en) * 1985-06-17 1987-03-03 Sperry Corporation Compliant lead clip
US4739125A (en) * 1985-09-27 1988-04-19 Hitachi, Ltd. Electric component part having lead terminals
JPS63118262U (en) * 1987-01-23 1988-07-30
JPH0193745U (en) * 1987-12-16 1989-06-20
JPH0189752U (en) * 1988-12-08 1989-06-13
JPH0536275Y2 (en) * 1988-12-08 1993-09-14
JPH07122833A (en) * 1993-10-26 1995-05-12 Nec Corp Integrated circuit package
JP2016025298A (en) * 2014-07-24 2016-02-08 セイコーエプソン株式会社 Electronic component, method of manufacturing electronic component, electronic apparatus, and mobile
JP2016139790A (en) * 2015-01-26 2016-08-04 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and mounting board thereof

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