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JPS57162200A - Doubling system for memory device - Google Patents

Doubling system for memory device

Info

Publication number
JPS57162200A
JPS57162200A JP56047373A JP4737381A JPS57162200A JP S57162200 A JPS57162200 A JP S57162200A JP 56047373 A JP56047373 A JP 56047373A JP 4737381 A JP4737381 A JP 4737381A JP S57162200 A JPS57162200 A JP S57162200A
Authority
JP
Japan
Prior art keywords
bit
doubling
permitted
entry
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56047373A
Other languages
Japanese (ja)
Inventor
Kazuo Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56047373A priority Critical patent/JPS57162200A/en
Publication of JPS57162200A publication Critical patent/JPS57162200A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To utilize storing spaces effectively by making a customer specify and change a doubling area by himself without the fixation of the area by the manufacture of the entitled device. CONSTITUTION:Each of memory units U0-U3 is divided into 4 storage blocks 0-3 and has the addresses of 128K (K=1,024) and data can be read/written from/in each memory unit independently. Four address conversion tables C0- C3 have entires in the units of 16 logical memory blocks fixed by continuous upper address bits A0-A3 started from the upper-most bit A0 and each entry has a doubling bit M, a valid bid V and a block bit M. At the normal operation, data in an entry are read out from one address conversion table to 4 logical circuits B0-B3. When double writing is permitted, 2 pairs of block specification signals BON-B3N and B1N-B2N are generated and, when not permitted, a pair of block specification signals are generated.
JP56047373A 1981-03-31 1981-03-31 Doubling system for memory device Pending JPS57162200A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047373A JPS57162200A (en) 1981-03-31 1981-03-31 Doubling system for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047373A JPS57162200A (en) 1981-03-31 1981-03-31 Doubling system for memory device

Publications (1)

Publication Number Publication Date
JPS57162200A true JPS57162200A (en) 1982-10-05

Family

ID=12773294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047373A Pending JPS57162200A (en) 1981-03-31 1981-03-31 Doubling system for memory device

Country Status (1)

Country Link
JP (1) JPS57162200A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125750A (en) * 1990-09-18 1992-04-27 Fujitsu Ltd Shared memory duplexing system
US5890218A (en) * 1990-09-18 1999-03-30 Fujitsu Limited System for allocating and accessing shared storage using program mode and DMA mode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125750A (en) * 1990-09-18 1992-04-27 Fujitsu Ltd Shared memory duplexing system
US5890218A (en) * 1990-09-18 1999-03-30 Fujitsu Limited System for allocating and accessing shared storage using program mode and DMA mode
US5963976A (en) * 1990-09-18 1999-10-05 Fujitsu Limited System for configuring a duplex shared storage

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