JPS57152753A - Packet editing system - Google Patents
Packet editing systemInfo
- Publication number
- JPS57152753A JPS57152753A JP56037817A JP3781781A JPS57152753A JP S57152753 A JPS57152753 A JP S57152753A JP 56037817 A JP56037817 A JP 56037817A JP 3781781 A JP3781781 A JP 3781781A JP S57152753 A JPS57152753 A JP S57152753A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- pkttr
- signal
- contents
- lim
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To reduce the soft processing, by writing terminating side information to headers in respect to packets for which rewriting of contents of a call control memory LIM except call set and release is unnecessary when packets are inputted to a packet transaction (PKTTR). CONSTITUTION:When a packet comes, a start signal ST is inputted to a controller DMACTL to start the transfer of the packet to the PKTTR. A signal REO is issued from the controller DMACTL to transfer the packet in byte units. First, the first byte is set to a register RO, and it is discriminated whether rewriting of the header is necessary or not. If unnecessary, the signal REO and a count signal WCU of a write address counter WAC are issued to write the packet to the PKTTR as it is. If rewriting of the header is necessary, the third and the fourth bytes are set to registers R1 and R2 on a basis of the count value of a byte counter (BCNT) at set timings (S1 and S2) generated from a timer TIM, and contents of the LIM corresponding to these addresses are referred to. Thus, contents of the LIM are rewritten.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56037817A JPS57152753A (en) | 1981-03-18 | 1981-03-18 | Packet editing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56037817A JPS57152753A (en) | 1981-03-18 | 1981-03-18 | Packet editing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57152753A true JPS57152753A (en) | 1982-09-21 |
Family
ID=12508071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56037817A Pending JPS57152753A (en) | 1981-03-18 | 1981-03-18 | Packet editing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57152753A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59198045A (en) * | 1983-04-25 | 1984-11-09 | Toyota Motor Corp | Multiplex transmitter of signal |
JPH0856239A (en) * | 1994-08-12 | 1996-02-27 | Nec Corp | D-channel packet communication system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51138103A (en) * | 1975-05-09 | 1976-11-29 | Western Electric Co | Packet exchanger |
-
1981
- 1981-03-18 JP JP56037817A patent/JPS57152753A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51138103A (en) * | 1975-05-09 | 1976-11-29 | Western Electric Co | Packet exchanger |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59198045A (en) * | 1983-04-25 | 1984-11-09 | Toyota Motor Corp | Multiplex transmitter of signal |
JPH0856239A (en) * | 1994-08-12 | 1996-02-27 | Nec Corp | D-channel packet communication system |
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