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JPS57121244A - Evaluating method for wafer - Google Patents

Evaluating method for wafer

Info

Publication number
JPS57121244A
JPS57121244A JP638581A JP638581A JPS57121244A JP S57121244 A JPS57121244 A JP S57121244A JP 638581 A JP638581 A JP 638581A JP 638581 A JP638581 A JP 638581A JP S57121244 A JPS57121244 A JP S57121244A
Authority
JP
Japan
Prior art keywords
wafer
photo resist
inspected
evaluation
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP638581A
Other languages
Japanese (ja)
Inventor
Noboru Tatefuru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP638581A priority Critical patent/JPS57121244A/en
Publication of JPS57121244A publication Critical patent/JPS57121244A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To reduce cost of a semiconductor device by a method wherein an evaluation on a wafer is performed without any wasted wafers by utilization of a non-destructive test method. CONSTITUTION:Several numbers of wafer are picked up among a lot of wafers on which semiconductor elements and oxide films are formed. Subsequently except several blocks 8 among a number of circuit element blocks which is arranged in column and row on a wafer 1, the surface of the wafer 1 is covered with a photo resist 7. Next by using an etching solution for detecting crystal defects the surface of the wafer 1 is etched. Next the surface of the wafer in the testing region 8 is inspected by a microscope, and existence of etched pits due to crystal defects in silicon and their distributions are inspected, and evaluation and judgment whether the wafer is good or bad is performed. If the wafer is defective, it is discarded and if it is acceptable, the photo resist film on the wafer is removed and restoration to the former wafer group is performed. By this method the circuit block covered with the photo resist 7 can be used without any break therein.
JP638581A 1981-01-21 1981-01-21 Evaluating method for wafer Pending JPS57121244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP638581A JPS57121244A (en) 1981-01-21 1981-01-21 Evaluating method for wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP638581A JPS57121244A (en) 1981-01-21 1981-01-21 Evaluating method for wafer

Publications (1)

Publication Number Publication Date
JPS57121244A true JPS57121244A (en) 1982-07-28

Family

ID=11636905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP638581A Pending JPS57121244A (en) 1981-01-21 1981-01-21 Evaluating method for wafer

Country Status (1)

Country Link
JP (1) JPS57121244A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252441A (en) * 1985-08-31 1987-03-07 Sumitomo Electric Ind Ltd Method for measuring crystal face azimuth of silicon wafer
EP0618615A1 (en) * 1993-03-31 1994-10-05 Siemens Aktiengesellschaft Method of defect determination and defect engineering on product wafers of advanced submicron technologies

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252441A (en) * 1985-08-31 1987-03-07 Sumitomo Electric Ind Ltd Method for measuring crystal face azimuth of silicon wafer
EP0618615A1 (en) * 1993-03-31 1994-10-05 Siemens Aktiengesellschaft Method of defect determination and defect engineering on product wafers of advanced submicron technologies
US5576223A (en) * 1993-03-31 1996-11-19 Siemens Aktiengesellschaft Method of defect determination and defect engineering on product wafer of advanced submicron technologies

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