JPS5696530A - Driving circuit of tri-state type - Google Patents
Driving circuit of tri-state typeInfo
- Publication number
- JPS5696530A JPS5696530A JP17583380A JP17583380A JPS5696530A JP S5696530 A JPS5696530 A JP S5696530A JP 17583380 A JP17583380 A JP 17583380A JP 17583380 A JP17583380 A JP 17583380A JP S5696530 A JPS5696530 A JP S5696530A
- Authority
- JP
- Japan
- Prior art keywords
- mos
- output
- signal
- terminal
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce occupied area and to enable high-speed drive, by providing a C-MOS inverter circuit between an output inverter circuit and logic circuits as a buffer. CONSTITUTION:C-MOS inverters 10, 11 are provided between output inverter circuits 8, 9 and logic circuits 12, 13. When a chip-enable signal CS is at high level, MOS-FETs 121, 131 are off and 122, 132 are on, and if the input signal to a terminal 1 is 0, the output signal at the terminal 2 is 0, and if the input signal is 1, then the output signal is 1. On the other hand, when the signal CS is at a low level, FETs 121, 131 are on and 122, 123 are off, and the output of C-MOS circuits (121, 122) (131, 132) is set always to 1 to cause cut off the base of the transistor 8 and the gate of MOS-FET 9. Thus, the output terminal 2 is floated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17583380A JPS5696530A (en) | 1980-12-15 | 1980-12-15 | Driving circuit of tri-state type |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17583380A JPS5696530A (en) | 1980-12-15 | 1980-12-15 | Driving circuit of tri-state type |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15557077A Division JPS5490941A (en) | 1977-12-26 | 1977-12-26 | Driving circuit of tristate type |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59110725A Division JPS6068718A (en) | 1984-06-01 | 1984-06-01 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5696530A true JPS5696530A (en) | 1981-08-04 |
JPS626370B2 JPS626370B2 (en) | 1987-02-10 |
Family
ID=16003008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17583380A Granted JPS5696530A (en) | 1980-12-15 | 1980-12-15 | Driving circuit of tri-state type |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5696530A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61224621A (en) * | 1985-03-29 | 1986-10-06 | Toshiba Corp | Tri-state buffer circuit |
JPS61270916A (en) * | 1985-05-27 | 1986-12-01 | Toshiba Corp | Tri-state driver circuit |
JPH05167430A (en) * | 1991-12-12 | 1993-07-02 | Nec Corp | Semiconductor logic circuit |
JPH0689585A (en) * | 1993-01-13 | 1994-03-29 | Hitachi Ltd | Semiconductor memory |
JPH08265134A (en) * | 1995-12-28 | 1996-10-11 | Hitachi Ltd | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5040977A (en) * | 1973-08-14 | 1975-04-15 |
-
1980
- 1980-12-15 JP JP17583380A patent/JPS5696530A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5040977A (en) * | 1973-08-14 | 1975-04-15 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61224621A (en) * | 1985-03-29 | 1986-10-06 | Toshiba Corp | Tri-state buffer circuit |
JPS61270916A (en) * | 1985-05-27 | 1986-12-01 | Toshiba Corp | Tri-state driver circuit |
JPH0431443B2 (en) * | 1985-05-27 | 1992-05-26 | ||
JPH05167430A (en) * | 1991-12-12 | 1993-07-02 | Nec Corp | Semiconductor logic circuit |
JPH0689585A (en) * | 1993-01-13 | 1994-03-29 | Hitachi Ltd | Semiconductor memory |
JPH08265134A (en) * | 1995-12-28 | 1996-10-11 | Hitachi Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS626370B2 (en) | 1987-02-10 |
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