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JPS5680899A - Error amending processing system of memory device - Google Patents

Error amending processing system of memory device

Info

Publication number
JPS5680899A
JPS5680899A JP15785679A JP15785679A JPS5680899A JP S5680899 A JPS5680899 A JP S5680899A JP 15785679 A JP15785679 A JP 15785679A JP 15785679 A JP15785679 A JP 15785679A JP S5680899 A JPS5680899 A JP S5680899A
Authority
JP
Japan
Prior art keywords
bit
register
content
output
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15785679A
Other languages
Japanese (ja)
Inventor
Satoru Nagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15785679A priority Critical patent/JPS5680899A/en
Publication of JPS5680899A publication Critical patent/JPS5680899A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To prevent deterioration of availability of a system by maintaining a fixed failure bit position in a memory and actuating an error amending function being amended beforehand.
CONSTITUTION: When 0 address of a memory device 1 is made access, the content thereof is fed to an error amending processing circuit 8 through a register 7, and when the data is correct, it is amended as it is and output to a register 9 and when it is not correct in the circuit 8, 1 bit error is detected and amended and output to the register 9. In addition to the fixed failure of a chip, a soft failure is produced in k bit at 0 address and accessed under two bit error condition, and then, the content of the register 7 fed through AND circuit 11, and the content of the register 10 read from the fixed failure bit position information memory 3, take an exclusive OR logic correspondingly to the bit in a bit corresponding conversion processing circuit 12. Therefore, it is returned to a correct value and with reference to k bit, since the corresponding value in the content of the register 10 is 0, it is not converted but output to the reigster 13 and the circuit 8 carries out 1 bit amendment and is output to the register 9.
COPYRIGHT: (C)1981,JPO&Japio
JP15785679A 1979-12-05 1979-12-05 Error amending processing system of memory device Pending JPS5680899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15785679A JPS5680899A (en) 1979-12-05 1979-12-05 Error amending processing system of memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15785679A JPS5680899A (en) 1979-12-05 1979-12-05 Error amending processing system of memory device

Publications (1)

Publication Number Publication Date
JPS5680899A true JPS5680899A (en) 1981-07-02

Family

ID=15658861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15785679A Pending JPS5680899A (en) 1979-12-05 1979-12-05 Error amending processing system of memory device

Country Status (1)

Country Link
JP (1) JPS5680899A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014120195A (en) * 2012-12-12 2014-06-30 Hgst Netherlands B V Method for encoding and decoding with use of combination number system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014120195A (en) * 2012-12-12 2014-06-30 Hgst Netherlands B V Method for encoding and decoding with use of combination number system

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