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JPS5654078A - Solar battery - Google Patents

Solar battery

Info

Publication number
JPS5654078A
JPS5654078A JP13048179A JP13048179A JPS5654078A JP S5654078 A JPS5654078 A JP S5654078A JP 13048179 A JP13048179 A JP 13048179A JP 13048179 A JP13048179 A JP 13048179A JP S5654078 A JPS5654078 A JP S5654078A
Authority
JP
Japan
Prior art keywords
amorphous semiconductor
convex
concave
solar battery
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13048179A
Other languages
Japanese (ja)
Inventor
Toshihiko Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13048179A priority Critical patent/JPS5654078A/en
Publication of JPS5654078A publication Critical patent/JPS5654078A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/30Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
    • H10F19/31Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
    • H10F19/35Structures for the connecting of adjacent photovoltaic cells, e.g. interconnections or insulating spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00Constructional details of devices covered by this subclass
    • H10F77/10Semiconductor bodies
    • H10F77/16Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/169Thin semiconductor films on metallic or insulating substrates
    • H10F77/1692Thin semiconductor films on metallic or insulating substrates the films including only Group IV materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To simplify a connecting method by a mechanism wherein when a plurality of solar battery consisting of semiconductor thin films are formed on an insulator substrate, a P type layer formed on a concave and an N type layer formed on a convex surface are directly touched with each other, using an uneven and stepped substrate as a base. CONSTITUTION:A substrate made concavo-convex steps is used as an insultor substrate 301, and on the first concave, a P type amorphous semiconductor 303a, an intrinsic amorphous semiconductor 302a and an N type amorphous semiconductor 304a are laminatingly formed to construct one solar battery. Then, on the convex adjacent to the concave, is provided one solar battery composed of a P type amorphous semiconductor 303b, an intrinsic amorphous semiconductor 302b and N type amorphous semiconductor 304b, and an end of the highest layer 304a of the concave and an end of the lowest layer 303b of the convex are brought in contact, by using the concavo-convex steps. In such a manner, individual solar batteries are connected in series and the solar batteries formed on the same plane of the convex are insulated by means of an insulating film 306 and at the same time, connected through a conductive layer 305 attached to the insulating film 306.
JP13048179A 1979-10-09 1979-10-09 Solar battery Pending JPS5654078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13048179A JPS5654078A (en) 1979-10-09 1979-10-09 Solar battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13048179A JPS5654078A (en) 1979-10-09 1979-10-09 Solar battery

Publications (1)

Publication Number Publication Date
JPS5654078A true JPS5654078A (en) 1981-05-13

Family

ID=15035278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13048179A Pending JPS5654078A (en) 1979-10-09 1979-10-09 Solar battery

Country Status (1)

Country Link
JP (1) JPS5654078A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759310B2 (en) * 1997-12-26 2004-07-06 Sony Corporation Method for making a semiconductor substrate comprising a variant porous layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759310B2 (en) * 1997-12-26 2004-07-06 Sony Corporation Method for making a semiconductor substrate comprising a variant porous layer

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