JPS56115553A - Method of mounting integrated circuit - Google Patents
Method of mounting integrated circuitInfo
- Publication number
- JPS56115553A JPS56115553A JP1951480A JP1951480A JPS56115553A JP S56115553 A JPS56115553 A JP S56115553A JP 1951480 A JP1951480 A JP 1951480A JP 1951480 A JP1951480 A JP 1951480A JP S56115553 A JPS56115553 A JP S56115553A
- Authority
- JP
- Japan
- Prior art keywords
- elements
- electrodes
- reference substrate
- substrate
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
PURPOSE:To mount a plurality of circuit elements in high density on the surface of a reference substrate by bonding the elements to the surface of the substrate with adhesive resin, filling the resin among the elements, then bonding a supporting plate onto the elements, removing the reference substrate to expose the elements, and wiring between the electrodes. CONSTITUTION:Thermally or chemically soluble adhesive resin 2 such as wax or photoresist for the semiconductor is covered on the reference substrate 1 formed of glass plate, and a plurality of IC chips 3 are bonded to confront the reference substrate. Thereafter, an insulating frame 4 in which a plurality of leading electrodes 5 are arranged is so bonded as to surround the IC chips so that the surfaces of the electrodes confront the substrate, and curable adhesive resin 6 is filled therein. The supporting plate 7 is placed thereon, and fixed to the frame 4. After the resin 6 is cured, the adhesive 2 is dissolved and removed, the reference substrate is removed to exposed the surface 3 of the elements, and the electrodes are wired therebetween. Thus, a large scale IC mounted with the elements in high density and reduced in size can be manufactured.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1951480A JPS56115553A (en) | 1980-02-18 | 1980-02-18 | Method of mounting integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1951480A JPS56115553A (en) | 1980-02-18 | 1980-02-18 | Method of mounting integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56115553A true JPS56115553A (en) | 1981-09-10 |
Family
ID=12001461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1951480A Pending JPS56115553A (en) | 1980-02-18 | 1980-02-18 | Method of mounting integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56115553A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58184753A (en) * | 1982-04-23 | 1983-10-28 | Clarion Co Ltd | Composite semiconductor device |
JPS58212154A (en) * | 1982-06-04 | 1983-12-09 | Clarion Co Ltd | Manufacture of semiconductor device |
JPS6142943A (en) * | 1984-08-06 | 1986-03-01 | Clarion Co Ltd | Manufacture of complex semiconductor device |
US5125153A (en) * | 1989-11-09 | 1992-06-30 | Oerlikon-Contraves Ag | Method of making a hybrid electronic array |
JP2010538463A (en) * | 2007-08-29 | 2010-12-09 | フリースケール セミコンダクター インコーポレイテッド | Interconnects in multi-element packages |
JP2016058464A (en) * | 2014-09-08 | 2016-04-21 | 日本電気株式会社 | Module component and manufacturing method of the same |
-
1980
- 1980-02-18 JP JP1951480A patent/JPS56115553A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58184753A (en) * | 1982-04-23 | 1983-10-28 | Clarion Co Ltd | Composite semiconductor device |
JPH0234465B2 (en) * | 1982-04-23 | 1990-08-03 | Clarion Co Ltd | |
JPS58212154A (en) * | 1982-06-04 | 1983-12-09 | Clarion Co Ltd | Manufacture of semiconductor device |
JPH0376027B2 (en) * | 1982-06-04 | 1991-12-04 | Clarion Co Ltd | |
JPS6142943A (en) * | 1984-08-06 | 1986-03-01 | Clarion Co Ltd | Manufacture of complex semiconductor device |
US5125153A (en) * | 1989-11-09 | 1992-06-30 | Oerlikon-Contraves Ag | Method of making a hybrid electronic array |
JP2010538463A (en) * | 2007-08-29 | 2010-12-09 | フリースケール セミコンダクター インコーポレイテッド | Interconnects in multi-element packages |
JP2016058464A (en) * | 2014-09-08 | 2016-04-21 | 日本電気株式会社 | Module component and manufacturing method of the same |
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