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JPS5539993A - Input-output controller - Google Patents

Input-output controller

Info

Publication number
JPS5539993A
JPS5539993A JP11393578A JP11393578A JPS5539993A JP S5539993 A JPS5539993 A JP S5539993A JP 11393578 A JP11393578 A JP 11393578A JP 11393578 A JP11393578 A JP 11393578A JP S5539993 A JPS5539993 A JP S5539993A
Authority
JP
Japan
Prior art keywords
input
output
circuit
write
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11393578A
Other languages
Japanese (ja)
Other versions
JPS6124737B2 (en
Inventor
Toshihiko Hiraide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11393578A priority Critical patent/JPS5539993A/en
Publication of JPS5539993A publication Critical patent/JPS5539993A/en
Publication of JPS6124737B2 publication Critical patent/JPS6124737B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To reduce the number of steps and execution time of a program in a data processor by allowing an input-output controller to control the write and use of control blocks and the read of statuses, and also to supervise the surplusage of the number of reads and that of writes.
CONSTITUTION: On the execution of a buffer control block information output instruction by data processor 2, input-output controller 1 sets control information to buffer control circuit 20; on the execution of a transfer start instruction, the memory location and input-output transfer of main memory unit 3 assigned by circuit 20 are performed by transfer control circuit 21 and data are inputted or outputted to or from input-output device 4 through input-output control circuit 22. In circuit 20, a write address and read address indicating storage positions of transfer control information are increased and decreased by one on each read operation and write operation. Then, circuit 20 sends information inhibiting the write operation when the write address exceeds the total number of storage positions, or information inhibiting the read operation when the storage position of the read address is subtracted one by one down to zero to data processor 2.
COPYRIGHT: (C)1980,JPO&Japio
JP11393578A 1978-09-14 1978-09-14 Input-output controller Granted JPS5539993A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11393578A JPS5539993A (en) 1978-09-14 1978-09-14 Input-output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11393578A JPS5539993A (en) 1978-09-14 1978-09-14 Input-output controller

Publications (2)

Publication Number Publication Date
JPS5539993A true JPS5539993A (en) 1980-03-21
JPS6124737B2 JPS6124737B2 (en) 1986-06-12

Family

ID=14624876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11393578A Granted JPS5539993A (en) 1978-09-14 1978-09-14 Input-output controller

Country Status (1)

Country Link
JP (1) JPS5539993A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731024A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Command processing system
JPS58129628A (en) * 1982-01-29 1983-08-02 Nec Corp Data channel device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (en) * 1973-02-23 1974-10-26
JPS53100744A (en) * 1977-02-16 1978-09-02 Hitachi Ltd Buffer control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (en) * 1973-02-23 1974-10-26
JPS53100744A (en) * 1977-02-16 1978-09-02 Hitachi Ltd Buffer control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731024A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Command processing system
JPS58129628A (en) * 1982-01-29 1983-08-02 Nec Corp Data channel device

Also Published As

Publication number Publication date
JPS6124737B2 (en) 1986-06-12

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