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JPS5532264A - Diagnostic system for memory unit - Google Patents

Diagnostic system for memory unit

Info

Publication number
JPS5532264A
JPS5532264A JP10452078A JP10452078A JPS5532264A JP S5532264 A JPS5532264 A JP S5532264A JP 10452078 A JP10452078 A JP 10452078A JP 10452078 A JP10452078 A JP 10452078A JP S5532264 A JPS5532264 A JP S5532264A
Authority
JP
Japan
Prior art keywords
circuit
unit
address
error
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10452078A
Other languages
Japanese (ja)
Inventor
Shozo Taniguchi
Osamu Araya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10452078A priority Critical patent/JPS5532264A/en
Publication of JPS5532264A publication Critical patent/JPS5532264A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Facsimile Transmission Control (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To use error corrected data rapidly and effectively by making the error diagnosis of data while a data processor attains no access and then by storing corrected data and error address.
CONSTITUTION: Control circuit 45 of diagnostic unit 40 detects the idle time for access to 1st memory circuit 30 via control circuit 20 of unit 40 by a control signal from unit 40 and then attains access to circuit 30 via circuit 20. Consequently, data read out from circuit 20 are diagnosed by data check circuit 41 of unit 40 and when an error is found, corrected data are stored in 2nd memory circuit 46 via error correction circuit 42. The address of the corrected data is stored in error address register 43 by way of circuits 30 and 45. When address comparator circuit 44 detects a coincidence between this address and that of circuit 30 by unit 10, the address of circuit 30 is not assigned via circuit 45 and the corrected data in circuit 46 are read out and transferred to unit 10.
COPYRIGHT: (C)1980,JPO&Japio
JP10452078A 1978-08-28 1978-08-28 Diagnostic system for memory unit Pending JPS5532264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10452078A JPS5532264A (en) 1978-08-28 1978-08-28 Diagnostic system for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10452078A JPS5532264A (en) 1978-08-28 1978-08-28 Diagnostic system for memory unit

Publications (1)

Publication Number Publication Date
JPS5532264A true JPS5532264A (en) 1980-03-06

Family

ID=14382758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10452078A Pending JPS5532264A (en) 1978-08-28 1978-08-28 Diagnostic system for memory unit

Country Status (1)

Country Link
JP (1) JPS5532264A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021033725A (en) * 2019-08-27 2021-03-01 三菱電機株式会社 Method of diagnosing dram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021033725A (en) * 2019-08-27 2021-03-01 三菱電機株式会社 Method of diagnosing dram

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