JPS551658A - Parity inspection unit - Google Patents
Parity inspection unitInfo
- Publication number
- JPS551658A JPS551658A JP7461878A JP7461878A JPS551658A JP S551658 A JPS551658 A JP S551658A JP 7461878 A JP7461878 A JP 7461878A JP 7461878 A JP7461878 A JP 7461878A JP S551658 A JPS551658 A JP S551658A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- area
- designates
- signal
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To enable to use effectively the memories by avoiding unnecessary use of memories, through the provision of exclusive memory area for parity bit.
CONSTITUTION: In case of 1K byte memory using memories of one chip 8-bit length, the number of bytes is 1024. The memory entire area is divided equally into eight, areas E0 to E7 so that the number of bytes in each area can be 128 bytes. The areas E0 to E6 are used as the data area and the area E7 is used as the parity bit area. On the other hand, the address designation signal of memory uses the signal of 10- bit, 0 to 9 bit. The signal for the upper rank 3-bit designates the areas E0 to E7, and the signal at the lower rank 7-bit designates 128 sets of words. The upper rank 3-bit of the data address designation signal designates the bit position and the lower 7-bit designates the word, allowing to designate the parity bit position corresponding to the data.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7461878A JPS551658A (en) | 1978-06-20 | 1978-06-20 | Parity inspection unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7461878A JPS551658A (en) | 1978-06-20 | 1978-06-20 | Parity inspection unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS551658A true JPS551658A (en) | 1980-01-08 |
JPS6110861B2 JPS6110861B2 (en) | 1986-03-31 |
Family
ID=13552333
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7461878A Granted JPS551658A (en) | 1978-06-20 | 1978-06-20 | Parity inspection unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS551658A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214040A (en) * | 1985-03-20 | 1986-09-22 | Fujitsu Ltd | Parity circuit of memory |
JPS6262360U (en) * | 1985-10-04 | 1987-04-17 | ||
JPH01140256A (en) * | 1987-11-26 | 1989-06-01 | Fujitsu Ltd | Memory parity checking method |
JPH03184146A (en) * | 1989-12-13 | 1991-08-12 | Fujitsu General Ltd | Parity check method |
-
1978
- 1978-06-20 JP JP7461878A patent/JPS551658A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214040A (en) * | 1985-03-20 | 1986-09-22 | Fujitsu Ltd | Parity circuit of memory |
JPS6262360U (en) * | 1985-10-04 | 1987-04-17 | ||
JPH01140256A (en) * | 1987-11-26 | 1989-06-01 | Fujitsu Ltd | Memory parity checking method |
JPH03184146A (en) * | 1989-12-13 | 1991-08-12 | Fujitsu General Ltd | Parity check method |
Also Published As
Publication number | Publication date |
---|---|
JPS6110861B2 (en) | 1986-03-31 |
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