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JPS5493939A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS5493939A
JPS5493939A JP61778A JP61778A JPS5493939A JP S5493939 A JPS5493939 A JP S5493939A JP 61778 A JP61778 A JP 61778A JP 61778 A JP61778 A JP 61778A JP S5493939 A JPS5493939 A JP S5493939A
Authority
JP
Japan
Prior art keywords
interruption request
interruption
line
clock
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61778A
Other languages
Japanese (ja)
Inventor
Kenichi Ooyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP61778A priority Critical patent/JPS5493939A/en
Publication of JPS5493939A publication Critical patent/JPS5493939A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To secure an interruption control system which can perform the processing based on the sequence of the interruption request.
CONSTITUTION: Central control center C and terminal unit T are connected to each other via bit clock line 3, character clock line 4 and interruption signal 5 each. The bit clock and the character clock are sent to line 3 and 4 from C, and units T are scanned in sequence to check the interruption request of T. In case the interruption request is given, the interruption request of the terminal unit is transmitted via line 5 and in the timing with which the bit clock controlled by the character clock is designated. Central control center C checks from which T the above mentioned interruption request is transmitted in the designated timing and then processes the interruption request.
COPYRIGHT: (C)1979,JPO&Japio
JP61778A 1978-01-06 1978-01-06 Interruption control system Pending JPS5493939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61778A JPS5493939A (en) 1978-01-06 1978-01-06 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61778A JPS5493939A (en) 1978-01-06 1978-01-06 Interruption control system

Publications (1)

Publication Number Publication Date
JPS5493939A true JPS5493939A (en) 1979-07-25

Family

ID=11478680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61778A Pending JPS5493939A (en) 1978-01-06 1978-01-06 Interruption control system

Country Status (1)

Country Link
JP (1) JPS5493939A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226564A (en) * 1985-07-26 1987-02-04 Nec Corp Processor system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940837A (en) * 1972-08-25 1974-04-17
JPS50156335A (en) * 1974-06-05 1975-12-17
JPS5239334A (en) * 1975-09-25 1977-03-26 Hitachi Ltd Interrupt processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940837A (en) * 1972-08-25 1974-04-17
JPS50156335A (en) * 1974-06-05 1975-12-17
JPS5239334A (en) * 1975-09-25 1977-03-26 Hitachi Ltd Interrupt processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226564A (en) * 1985-07-26 1987-02-04 Nec Corp Processor system

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