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JPS5467372A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5467372A
JPS5467372A JP13343377A JP13343377A JPS5467372A JP S5467372 A JPS5467372 A JP S5467372A JP 13343377 A JP13343377 A JP 13343377A JP 13343377 A JP13343377 A JP 13343377A JP S5467372 A JPS5467372 A JP S5467372A
Authority
JP
Japan
Prior art keywords
film
pattern
wiring
region
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13343377A
Other languages
Japanese (ja)
Inventor
Ryosaku Kanzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13343377A priority Critical patent/JPS5467372A/en
Publication of JPS5467372A publication Critical patent/JPS5467372A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To facilitate opening of Si3N4 film poor in workability, by providing a lift-off pattern on an Al wiring formed on a semiconductor substrate, depositing SiO2 film and Si3N4 film, removing the pattern, amd forming an external electrode lead-out hole in the Al wiring.
CONSTITUTION: SiO2 film 3 is deposited on an Si substrate 1 in which an active region 2 is provided. An opening is cut in the region 2, and Al wiring 5 is evaporated on the entire surface while connecting with the region 2. In a specified region thereof is formed a lift-off pattern 6 of photo resist, polyimide or the like, and Si3N4 film 7 is grown on the entire surface by sputtering using N2 gas. Then the surface is covered with SiO2 film 8. Providing a photo resist pattern 9, an opening is made only in the film 8 by buffer etching, the pattern 9 and pattern 6 are lifted off together with the film 7 thereabove, and an external electrode lead-out hole 10 is produced in the wiring 5. Then, Al electrode 11 is provided in that place.
COPYRIGHT: (C)1979,JPO&Japio
JP13343377A 1977-11-09 1977-11-09 Production of semiconductor device Pending JPS5467372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13343377A JPS5467372A (en) 1977-11-09 1977-11-09 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13343377A JPS5467372A (en) 1977-11-09 1977-11-09 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5467372A true JPS5467372A (en) 1979-05-30

Family

ID=15104651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13343377A Pending JPS5467372A (en) 1977-11-09 1977-11-09 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5467372A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5750465A (en) * 1980-09-11 1982-03-24 Fujitsu Ltd Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5750465A (en) * 1980-09-11 1982-03-24 Fujitsu Ltd Semiconductor memory device

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