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JPS5467360A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5467360A
JPS5467360A JP13341377A JP13341377A JPS5467360A JP S5467360 A JPS5467360 A JP S5467360A JP 13341377 A JP13341377 A JP 13341377A JP 13341377 A JP13341377 A JP 13341377A JP S5467360 A JPS5467360 A JP S5467360A
Authority
JP
Japan
Prior art keywords
terminals
selection
signal
selection signal
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13341377A
Other languages
Japanese (ja)
Inventor
Kazuo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13341377A priority Critical patent/JPS5467360A/en
Publication of JPS5467360A publication Critical patent/JPS5467360A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To increase the noise margin relating to selection and to speed up the circuit operation, by constituting the amplitude of selection signal arbitrarily selectable, in a master-slave FF. CONSTITUTION:When the signal level fed to the sirst selection terminals a, b and second selection terminals c, d are increased than the level more for the terminals a, b than the terminals c, d, the first state is obtained, and if the level for the termianals c, d is higher than that of the terminals a, b, the second state is constitued. The two logic circuits constituted with transistors TrQ35, 36, 37, 38 are provided. Further, TrQ29 to Q34 inputting the selection signal Co to S from external and the voltage VBB and giving the selection signal to the logic circuit through the selection terminals a to d, load resistors Rx1, Ry1, Rx2 and Ry2 are connected in series with the collector, constituting the selection signal generation circuit. Further, by selecting the values of the resistors Rx1, Ry1, Rx2, Ry2 and arbitrarily selecting the amplitude of the signal given to the logic circuit, the potential of the driving points A to D is selected for the master slave type FF.
JP13341377A 1977-11-09 1977-11-09 Logic circuit Pending JPS5467360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13341377A JPS5467360A (en) 1977-11-09 1977-11-09 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13341377A JPS5467360A (en) 1977-11-09 1977-11-09 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5467360A true JPS5467360A (en) 1979-05-30

Family

ID=15104178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13341377A Pending JPS5467360A (en) 1977-11-09 1977-11-09 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5467360A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59212018A (en) * 1983-05-13 1984-11-30 ウエスターン・エレクトリツク・カムパニー，インコーポレーテツド Digital latch circuit
JPH0685621A (en) * 1992-02-12 1994-03-25 Nec Corp Latch circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59212018A (en) * 1983-05-13 1984-11-30 ウエスターン・エレクトリツク・カムパニー，インコーポレーテツド Digital latch circuit
JPH0685621A (en) * 1992-02-12 1994-03-25 Nec Corp Latch circuit

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