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JPS5453952A - Delay pulse generating circuit - Google Patents

Delay pulse generating circuit

Info

Publication number
JPS5453952A
JPS5453952A JP12009877A JP12009877A JPS5453952A JP S5453952 A JPS5453952 A JP S5453952A JP 12009877 A JP12009877 A JP 12009877A JP 12009877 A JP12009877 A JP 12009877A JP S5453952 A JPS5453952 A JP S5453952A
Authority
JP
Japan
Prior art keywords
voltage
capacitor
output
delay pulse
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12009877A
Other languages
Japanese (ja)
Inventor
Takusane Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12009877A priority Critical patent/JPS5453952A/en
Publication of JPS5453952A publication Critical patent/JPS5453952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Landscapes

  • Relay Circuits (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To enable the setting of the delay time, by providing the clamp circuit clamping the charging or discharge level of the capacitor to a given level. CONSTITUTION:When the charging level exceeds the reference voltage V2, the output Vc of the voltage comparator A3 is inverted into O. The output Vc of the voltage comparator A3 and the signal O when the switch SW is turned on make the output of the NOR circuit L1 in the clamp circuit 3 into 1, turning on the clamp transistor Q2. Thus, negative feedback is given to the capacitor terminal and the charge is made temporarily stopped by clamping the terminal voltage Vt of the capacitor C to the reference voltage of the voltage comparator A3. The capacitor terminal voltage Vt is detected with the voltage comparators A2 and A4 and the delay pulse Vo can be obtained.
JP12009877A 1977-10-07 1977-10-07 Delay pulse generating circuit Pending JPS5453952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12009877A JPS5453952A (en) 1977-10-07 1977-10-07 Delay pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12009877A JPS5453952A (en) 1977-10-07 1977-10-07 Delay pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS5453952A true JPS5453952A (en) 1979-04-27

Family

ID=14777854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12009877A Pending JPS5453952A (en) 1977-10-07 1977-10-07 Delay pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS5453952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122507A (en) * 1982-01-16 1983-07-21 Hitachi Ltd Pulse signal generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122507A (en) * 1982-01-16 1983-07-21 Hitachi Ltd Pulse signal generating circuit
JPH0544229B2 (en) * 1982-01-16 1993-07-05 Hitachi Ltd

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